David writes, > I'm old enough to remember the "Microsoft Certified Systems > Engineer" credential which was voided overnight by Microsoft > when the next version of Windows (?Windows 95) was released. > That matter was aired right here on Link, but fortunately I've never > been long in Microsoft Land (:-). David Lochrin
Good on you David :) And apparently, India intends to follow suite .. “In India, RISC-V Is the New Linux” By Christine Hall Dec 20 2023 https://fossforce.com/2023/12/in-india-risc-v-is-the-new-linux/ The Indian government intends for RISC-V, the open-source ISA, to be the cornerstone for building the country’s tech economy. The Indian tech site Analytics India Magazine just published a nice article by Pritam Bordoloi that equates what’s currently happening in India with RISC-V with what happened in the US when Linux came on the scene in the 1990s. If you don’t know, RISC-V is an open-source instruction set architecture that anyone can use to design and build anything from accelerators to full-blown CPUs. RISC-V chips can be used either to compete with the likes of Intel, AMD, Arm, and others — or to bypass them entirely to use silicon specifically designed to meet the the needs of their intended device. This does away with the trade-offs that are usually necessary when devices are designed around the capabilities and requirements of off-the-shelf chips. Bordoloi points out that RISC-V is behind something of a boom in homegrown chip development in developing countries with large tech economies, such as India, because it frees them from reliance on technology from large companies located mostly in the US and China. Not only does this save them money, it also helps the local economy by giving rise to a domestic chipmaking industry. It’s also a move towards economic independence, as technology developed in other countries are generally exported with a long list of regulations that are not only costly, but limit how the technology can be used. This issue had become more important in recent years, as both the US and China have moved to restrict exports of silicon technology, partly because of security concerns, but also to maintain a competitive edge in global markets. The threat of increasing restrictions, or of losing the availability to import the technology entirely, has led the India government to initiate the Digital RISC-V program, “which aims to foster the development of next-generation microprocessors within India, positioning the nation as a prominent global hub for RISC-V expertise,” according to Bordoloi. For this purpose, India needs to create a workforce of RISC-V specialist, which the DRV intends to do by creating 10,000 jobs within the next five years. -- You can read Bordoloi’s entire article here: “RISC-V is Creating a ‘Linux Movement’ in Hardware” https://analyticsindiamag.com/risc-v-is-creating-a-linux-movement-in-hardware/ By Pritam Bordoloi, Dec 28, 2023 “RISC-V is Creating a ‘Linux Movement’ in Hardware” India recognises the significant potential of RISC-V, envisioning it as a catalyst for establishing an robust chip design ecosystem in the country In 1991, when Linus Torvalds created Linux, an open-source operating system, it threatened Microsoft’s business as Linux was an alternative to one of its core products-Windows. The open-source nature of Linux allowed developers worldwide to contribute to its development, resulting in a robust and versatile operating system. Secondly, Linux’s stability, security, and scalability made it suitable for a wide range of applications, from personal computers to servers and embedded devices. It played a significant role in the open-source software movement, and even prompted former Microsoft CEO Steve Balmer to refer Linux as ‘cancer.’ Now, we are seeing a similar movement in hardware with RISC-V, an open-standard instruction set architecture (ISA) designed to be licence-free and royalty-free, allowing anyone to use, develop, manufacture, or sell RISC-V chips and software. RISC-V, which began as a project at UC Berkeley’s Parallel Computing Laboratory in 2010, is challenging Intel’s x86 and ARM architectures. For instance, a recent report from the Next Platform suggests that Meta is transitioning from traditional CPUs to RISC-based components. This shift is attributed to power efficiency, enhanced performance, reduced latency, and the adaptability to accommodate various workloads offered by the RISC-V. Meanwhile, India, too, recognises the significant potential of RISC-V, envisioning it as a catalyst for establishing a robust chip design ecosystem in the country. Making RISC-V the Indian ISA (Instruction Set Architecture) In pursuit of this objective, in April 2022, the Indian government initiated the Digital RISC-V programme ( DIR-V), which aims to foster the development of next-generation microprocessors within India, positioning the nation as a prominent global hub for RISC-V expertise. Union Minister Rajeev Chandrasekhar, who himself was a former chip designer, has also been actively involved in promoting and supporting the RISC-V architecture. “It is certainly our ambition as a country and with hundreds and thousands of engineers amongst the audience that we will master and become if not the global leader but certainly amongst the world’s leading nations in propagating and navigating the capabilities and capacities to create innovation around the RISC V and DIR V family of chips and systems. The government of India is fully committed to making DIR-V the Indian ISA (Instruction Set Architecture),” the minister said. India sees chip designing as one of its core strengths and is actively involved in the design of computing systems across various domains, including compute, industrial IoT, automotive, telecom, and wireless, as well as strategic technologies. The DIR-V processors are poised to drive systems in these diverse sectors, introducing healthy competition to other processor-based systems. “RISC-V is a tool or a framework that allows us to innovate quickly to satisfy the demand for well-designed chips. The fact that it is open source enables us to pick and choose between different extensions and implementations while remaining compatible with a well-defined standard,” said Shashwath T R, co-founder and CEO of Mindgrove Technologies. Developing a RISC-V ecosystem in India However, to build a robust RISC-V ecosystem in India, the country needs more companies to emerge in the space along with increased funding. Also, what the country needs is to create a workforce specialising in RISC-V architecture. The DIR-V programme aims to create over 10,000 jobs in the next five years. Besides, “We need more companies working on different aspects – both the silicon and associated areas such as verification, core and peripheral IP, physical design, etc., across every vertical that is relevant to India,” Shashwath said. To sustain the ecosystem, India also needs different parties building boards, development tools and software aspects such as compilers, debuggers, IDEs, etc. Moreover, the RISC-V and related specifications are developed, ratified and maintained by RISC-V International, a diverse membership base, including industry leaders, academic institutions, startups, and individuals. It has over 3,000 members, including major semiconductor companies, software providers, and system integrators in 70 countries. There’s a need for a strong presence in the decision-making levels of RISC-V International so that Indian concerns are addressed as a top priority. “Finally, we need to see massive adoption by our users – the companies and brands that build products based on our chips, and that comes back down to building compelling chips that they are happy to put into such products,” Shashwath said. An opportunity for Indian startups Nonetheless, the government’s focus on RISC-V does present an opportunity for Indian startups to innovate and fulfil the objectives of the DIR-V programme. Due to its open-source nature, it allows startups and entrepreneurs to build their own products without the need for expensive licensing fees. This openness provides Indian startups with the flexibility to innovate and customise their chip designs according to their specific requirements. Indian startups can leverage RISC-V to develop indigenous chip designs, contributing to the country’s self-reliance in semiconductor technology and, at the same time, serving global customers. “The fact that RISC-V is open, widely adopted by the industry, and built on the lessons learned from decades of experience in building microprocessors makes it a compelling standard for us to focus on. Not only is it significantly less expensive than using legacy ISAs, but our designers can also hit the road running with innovative designs and microarchitectures, software, and tools,” Shashwath said. Mindgrove’s first few products, according to Shashwath, were based on the RISC-V Shakti C-Class processor developed in the RISE lab at IIT Madras. Gani Subramaniam, senior partner at Celesta Capital, previously told AIM that RISC-V is driving the creation of new startups in India as well as more and more RISC-V startups getting funded in India. Chandrasekhar also emphasised that startups such as Mindgrove Technologies, Ventana MicroSystems, Esperanto Technologies, InCore Semiconductors and Morphing Machines have emerged for the DIR V ecosystem. Moreover, the government is also mulling acquiring equity stakes in the companies to nurture startups in the space. A more open architecture is safer because it allows independent researchers to red-team it and find all the holes that need to be plugged in. Independent contributors’ efforts in what made Linux a very secure system. “RISC-V benefits from the same idea, and there is a vibrant security community around RISC-V. In fact, the story of how Shakti came to be is precisely this – the team at IIT-M was looking for an architecture to conduct, among other things, security research. The closed-source ones did not allow them to do so without several restrictions, and hence Shakti was born,” Shashwath added. -------------- _______________________________________________ Link mailing list [email protected] https://mailman.anu.edu.au/mailman/listinfo/link
