> I recently attended an IBM "Executive Briefing" in Austin, > Texas, on IBM's > plans for the pSeries hardware. Nowhere did this come up. Just the > opposite. The pSeries folks were frankly in admiration of the zSeries > processors, and hoped to someday be in the same tier of > reliability with it. > The way this is being done within IBM is by combining the processor > development teams. There are now zSeries folks working on > pSeries, etc. > They're transferring a lot of the technology built into the > zSeries into the > Power line, primarily error recovery stuff that is on-chip, > but other things > as well. (Some of which I'm unsure I can talk about, so I > won't.) Their > main goal for the near future is to have as much error > recovery circuitry on > the processor as zSeries does (currently around 40% of the total).
I don't think the two are mutually exclusive. Adding microcoding capability would probably simplify some of the technical verification of the lower-level instruction set (and thus the problem becomes verification of the ucode running on that set, a problem that at least the zSeries folks already understand), and you can start playing with a lot of other stuff once the logical archicture is divorced from the physical implementation (gee, where have we heard that idea before??) -- db
