Phil, By themsleves the cycle times might not be of interest. The cycle times in conjunction with explanation of fetch operations and how instructions and their addresses are really resolved would probably be very instructive.
Not complex examples but a few that illustrate why a compare and swap is more reliable in a multi processor environment and an MVCL isn't. Paul -----Original Message----- From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Phil Payne Sent: Saturday, December 13, 2003 5:22 AM To: [EMAIL PROTECTED] Subject: Re: Technical Specs > Actually, I believe they do. Take the cycle time (which I believe > they do publish somewhere) and invert, and voila. I seem to recall > from some comments that Barton Robinson made many months ago that the > first generation zSeries boxes were 200Mhz machines (5ns cycle time). > I'm sure someone who knows for sure can confirm or refute that. IBM does publish cycle times in some of their "in depth" discussion of zSeries processor designs. However, there are so many other factors involved in zSeries performance that these are almost an aside in the discussion of the design. I have a list of cycle times for the last twenty or so mainframes announced including Amdahl and Hitachi products - I've never felt it worthwhile to publish them because they don't really add a great deal to our knowledge and they distract from the real factors. -- Phil Payne http://www.isham-research.com +44 7785 302 803
