On Tuesday, 12/16/2003 at 02:14 CET, Phil Payne <[EMAIL PROTECTED]> wrote: > > I imagined that MVC was "atomic" in nature meaning that the second processor > > couldn't "garble" things until the MVC had run it's course. > > I think that's "implementation-dependent", as IBM would say. Unwise to rely on it.
No, not implementation-dependent. Look in the PoP under "Consistency Specification". Subject to the documented initial conditions, MVC and MVCL will have consitency on each 4 or 8 bytes that are read and written. That means that the storage access to those locations is serialized and other CPUs will observe storage changing in 4- or 8-byte increments. As another example, (assuming 390 architecture mode) if you load all 16 registers with Load Multiple, and the operand address is on a word boundary, then registers will be loaded 2 at a time (doubleword) with consistency. Regs 0 & 1 will be consistent, 2 & 3, and so on. Alan Altmark Sr. Software Engineer IBM z/VM Development
