Richard Pinion wrote:
Richard
You may be posting in HTML. Better if you don't - shorter emails kinder
to dialup users, less likely to be tagged as spam (some people, would
you believe it? refuse HTML email altogether). It might explain why
Mozilla's quoting is a bit off.
I've always wanted to ask this question and you seem like someone who would
know. First and foremost I am not a computer engineer!
Here's the situation.
When the PC first came out I taught myself some basic assembler for the x86
chip. One thing that I remember to move 255 bytes from one location to another
I had to set up a count register, source register, and target register. The
move instruction was executed in a loop that decemented/incremented (I don't
remember which) the counter. While I'm sure there is a lot of stuff that
happens at the microcode level of the mainframe, we use one assembler
instruction to move 255 bytes. From what I remember of x86 assembler it took
more instructions to do things than it did on the mainframe. If the the x86
chip were faster than the mainframe's chip, would some of that speed be lost
because it takes more instructions to do the same task?
Common operations.
1. Add 1 to storage location
* S/370
la 0,1
a 0,storage
st 0,storage
# Intel
inc [storage]
2. Add 2 to storage location
* S/370 - Like above
# Intel
add [storage],2
3. Compute address
* S/370
la r15,address
# Intel
lea si,address
4. Subroutine call
* S/370 Depends on OS, maybe
la r1,parmlistaddress Note assumes parmlist already built
l r15,=v(subroutine)
basr r14,r15 Formerly balr r14,r15
# Intel
call subroutine # Note assumes args on stack, like parmlist above
5 Loops
* S/370
bxle and bxh which confuse nearly everyone:-)
# intel
loope, loopne
jcxz
rep # a prefix to repeat many individual instructions
Register usage on Intel is more confusing, but beware there are many
S/370 instructions that use two (or more) registers and can cause
confusion to the unwary.
I can't think of a good translation of S/370's test under mask.
I generally avoided BXH and BXLE because they are so confusing. Even if
I know what's going on, it's not certain my successor will.
I've not done significant assembler programming for XA; I always had to
be wary of LA and some other instructions' 24-bit results.
Addressing modes on Intel are more confusing, and instructions that look
alike other than the actual instruction(s) used can create
different-sized object code and have different timings. Again, my
knowledge of 8086-family CPUs is fairly dated, I've not looked at
anything more recent that 80386.
S/370 I/O leaves Intel for dead, you write a channel program (which is
generally quite simple) and tell a channel to run it. On Intel, the main
CPU has to do all the work, and it's quite complicated.
--
Cheers
John
-- spambait
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