On Sat, 2009-11-28 at 09:43 +0100, Martin Schwidefsky wrote:

> I don't see the connection between TLB misses and hiperdispatch. Could
> you elaborate please?

I (perhaps naively) believed that an operating system that had the
ability to request PR/SM only dispatch it on a CPU that was cache (and
TLB) "hot" might actually generate some benefit. The z/OS developers
seemed to think so.

Are you suggesting that running as a guest under z/VM on PR/SM
arbitrated hardware would *not* benefit from this ?. How about being
dispatched on an entirely different book (node from a NUMA perspective)
if the guest made the effort to ensure dispatch was "close" to the last
CPU used. I would think that having a hipervisor in between that lies to
its guest(s) can hardly be beneficial.
Maybe I'm just being too simplistic.

Shane ...

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