On 16.01.2018 14:43, Dan Skwire wrote: > So, it has been found that Intel, ARM, and other chips have these cache > operation failings. These are a result of lack of cleanup regarding the path > in “speculative execution” on those chips. System/z processors also use > “speculative execution”. Cache cleanups? Not publicly posted AFAIK.
I just crawled the Principles of Operation and the relevant instruction seems to be PREFETCH DATA (RELATIVE LONG). Code 7 is documented as "Release the cache line containing the second operand from all accesses". Luckily it is also documented that "PREFETCH DATA (RELATIVE LONG) signals the CPU to perform the specified operation, but it does not guarantee that the CPU will necessarily honor the request.". So I suppose a microcode update that disables the flushing is technically fair game. Kind regards Philipp Kern ---------------------------------------------------------------------- For LINUX-390 subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO LINUX-390 or visit http://www.marist.edu/htbin/wlvindex?LINUX-390 ---------------------------------------------------------------------- For more information on Linux on System z, visit http://wiki.linuxvm.org/
