James Manning wrote:
> [ Saturday, July 31, 1999 ] Edward Schernau wrote:
> > Hal Burgiss wrote:
> > > 'noapic' forces linux back to non-smp interrupts.
> >
> > But without disabling SMP? What other impacts does this have?
>
> Just routes all interrupts to the first CPU instead of distributing
> them... a later posts in the thread shows that... compare this to
> the APIC-enabled board below (note that unless interrupt-heavy in
> the extreme, it's doubtable that one CPU can't keep up with the
> load and spreading is necessary.)
>
> # cat /proc/interrupts
> CPU0 CPU1 CPU2 CPU3
> 0: 317360976 322526941 303606254 301038353 IO-APIC-edge timer
> 1: 88 94 103 75 IO-APIC-edge keyboard
> 2: 0 0 0 0 XT-PIC cascade
> 8: 1 0 0 0 IO-APIC-edge rtc
> 9: 13917998 13967812 13737924 13705736 IO-APIC-level Intel EtherExpress
>Pro 10/100 Ethernet
So, here you'd say that all 4* 13M interrupts would've been run on one
CPU, whereas you see that with io-apic, they are distributed. However
they wouldn't be "load-balanced" without the ioapic. Only different
interrupts would've been run on a different CPU concurrently.
> 10: 6537395 6544214 6536742 6533095 IO-APIC-level aic7xxx
So, only hte 4*6M scsi interrupts would've been able to run concurrently.
Note that this system has been up for 300M*4/100 = 12.7 M
seconds. It's seen 4*139M ethernet interrupts in that time, which
averages to 4.4 interrupts per second. That's really really low
interrupt rate.
The timer indeed is much more significant at 100 per second....
A pentium 120 can handle around 140k interrupts per second, so at 100
interrupts per second, about 1/1000th of the machine is used by
interrupts, so when the disk would use 100 interrupts per second, the
contention with the timer would cause about 1 in 1000 of performance
loss. (that is, extra latency. That doesn't even always translate into
performance loss!)
Roger.
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