on two dual C400 machines that i had previously trusted to be stable at
550M (92M FSB), i had some sobering experiences about how subtle OC
problems can be with SMP. both machines use QQ bios and enlight 7101
case (250W power supply), with not a lot of HW inside.
1) on a solaris8 install, the install failed copying itself to disk,
complaining of apic interrupt errors. at least it was up front about it,
and all was well back at boring old 400M.
2) on a rather complex java server application using the recently
blessed blackdown jdk1.2.2 and native threads, i get segment violations
using OC and none without.
my take: SMP w/ celeron is a clever but delicate hack involving a pullup
on a high frequency signal (anything over 50MHz is high). if we were
talking asynchronous systems, i'd be crying "synchronizer failure", but
these things are both clocked and frequency locked (oooh, and phase
locked loops *are* sensitive to noise).
getting SMP at all w/ celeron is a blessing. trying for more is maybe
going a little too far in the something-for-nothing direction.
kudos to abit for having the guts to produce this board. (and hey, where
is the dual chipzilla-approved fc-370 board?)
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