On Feb 21, 2008 1:50 AM, Jesse Barnes <[EMAIL PROTECTED]> wrote: > > I would like to know what they're for. > They're for saving and restoring GPU state across suspend/resume. They're > particularly useful if your machine doesn't re-POST at resume time. In that > case your GPU may be totally uninitialized, so either the kernel or X has to > set it up for you (X only does that partially).
Ok. A lot to digest. > Interesting, which chipset do you have? AFAIK that shouldn't cause a hang. (II) intel(0): Integrated Graphics Chipset: Intel(R) 945GM > I know I fixed that problem in at least one configuration... Can you try: > # echo test > /sys/power/disk > # echo disk > /sys/power/state > and see if that also turns your screen green? Yes, still green. But I got it to actual reboot with ... echo reboot > /sys/power/disk So, next I'll try "shutdown" to see if it work. I was using "platform". > Also, getting a GPU register dump would be helpful. The intel_reg_dumper tool Attached are the two dumps from console. One prior to suspend, and one after resume. Thanks, Jeff.
(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): CACHE_MODE_0: 0x00006820 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000077 (II): DSPARB: 0x00001d9c (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync) (II): LVDS: 0xc0000300 (enabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000001 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PFIT_CONTROL: 0x80002668 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000020 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0x00000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00000000 (0 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, single-wide) (II): PIPEASRC: 0x027f01df (640, 480) (II): PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x20000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x031f027f (640 active, 800 total) (II): HBLANK_A: 0x03170287 (648 start, 792 end) (II): HSYNC_A: 0x02ef028f (656 start, 752 end) (II): VTOTAL_A: 0x020c01df (480 active, 525 total) (II): VBLANK_A: 0x020401e7 (488 start, 517 end) (II): VSYNC_A: 0x01eb01e9 (490 start, 492 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x49000000 (disabled, pipe B) (II): DSPBSTRIDE: 0x00000280 (640 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x018f02cf (720, 400) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x80000000 (enabled, single-wide) (II): PIPEBSRC: 0x027f018f (640, 400) (II): PIPEBSTAT: 0x80000202 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS) (II): FPB0: 0x00020e09 (n = 2, m1 = 14, m2 = 9) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x98046003 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14, SDVO mult 1) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_B: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_B: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_B: 0x032502ff (768 active, 806 total) (II): VBLANK_B: 0x032502ff (768 start, 806 end) (II): VSYNC_B: 0x03080302 (771 start, 777 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0x22c4008e (enabled) (II): TV_CTL: 0x00000000 (II): TV_DAC: 0x70000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): MI_MODE: 0x00000220 (II): MI_DISPLAY_POWER_DOW: 0x0000007f (II): MI_ARB_STATE: 0x00000040 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): SR00: 0x03 (II): SR01: 0x00 (II): SR02: 0x03 (II): SR03: 0x00 (II): SR04: 0x02 (II): SR05: 0x00 (II): SR06: 0x00 (II): SR07: 0x00 (II): MSR: 0x67 (II): ARX: 0x20 (II): AR00: 0x00 (II): AR01: 0x01 (II): AR02: 0x02 (II): AR03: 0x03 (II): AR04: 0x04 (II): AR05: 0x05 (II): AR06: 0x06 (II): AR07: 0x07 (II): AR08: 0x08 (II): AR09: 0x09 (II): AR0a: 0x0a (II): AR0b: 0x0b (II): AR0c: 0x0c (II): AR0d: 0x0d (II): AR0e: 0x0e (II): AR0f: 0x0f (II): AR10: 0x0c (II): AR11: 0x00 (II): AR12: 0x0f (II): AR13: 0x08 (II): AR14: 0x00 (II): CR00: 0x5f (II): CR01: 0x4f (II): CR02: 0x50 (II): CR03: 0x82 (II): CR04: 0x55 (II): CR05: 0x81 (II): CR06: 0xbf (II): CR07: 0x1f (II): CR08: 0x00 (II): CR09: 0x4f (II): CR0a: 0x0d (II): CR0b: 0x0e (II): CR0c: 0x21 (II): CR0d: 0x20 (II): CR0e: 0x28 (II): CR0f: 0xa0 (II): CR10: 0x9c (II): CR11: 0x8e (II): CR12: 0x8f (II): CR13: 0x28 (II): CR14: 0x1f (II): CR15: 0x96 (II): CR16: 0xb9 (II): CR17: 0xa3 (II): CR18: 0xff (II): CR19: 0x00 (II): CR1a: 0x00 (II): CR1b: 0x00 (II): CR1c: 0x00 (II): CR1d: 0x00 (II): CR1e: 0x00 (II): CR1f: 0x00 (II): CR20: 0x00 (II): CR21: 0x00 (II): CR22: 0x20 (II): CR23: 0x00 (II): CR24: 0x80 (II): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10 (II): pipe B dot 54166 n 2 m1 14 m2 9 p1 3 p2 14 (II): DumpRegsEnd
(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): CACHE_MODE_0: 0x00006820 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000016 (II): DSPARB: 0x00001d9c (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync) (II): LVDS: 0xc0000300 (enabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000001 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PFIT_CONTROL: 0x80002668 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000020 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0x00000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00000000 (0 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, single-wide) (II): PIPEASRC: 0x027f01df (640, 480) (II): PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x20000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x031f027f (640 active, 800 total) (II): HBLANK_A: 0x03170287 (648 start, 792 end) (II): HSYNC_A: 0x02ef028f (656 start, 752 end) (II): VTOTAL_A: 0x020c01df (480 active, 525 total) (II): VBLANK_A: 0x020401e7 (488 start, 517 end) (II): VSYNC_A: 0x01eb01e9 (490 start, 492 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x49000000 (disabled, pipe B) (II): DSPBSTRIDE: 0x00000280 (640 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x018f02cf (720, 400) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x80000000 (enabled, single-wide) (II): PIPEBSRC: 0x027f018f (640, 400) (II): PIPEBSTAT: 0x80000242 (status: FIFO_UNDERRUN VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS) (II): FPB0: 0x00020e09 (n = 2, m1 = 14, m2 = 9) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x98046003 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14, SDVO mult 1) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_B: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_B: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_B: 0x032502ff (768 active, 806 total) (II): VBLANK_B: 0x032502ff (768 start, 806 end) (II): VSYNC_B: 0x03080302 (771 start, 777 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0x22c4008e (enabled) (II): TV_CTL: 0x00000000 (II): TV_DAC: 0x70000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): MI_MODE: 0x00000220 (II): MI_DISPLAY_POWER_DOW: 0x0000007f (II): MI_ARB_STATE: 0x00000040 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): SR00: 0x03 (II): SR01: 0x00 (II): SR02: 0x03 (II): SR03: 0x00 (II): SR04: 0x02 (II): SR05: 0x00 (II): SR06: 0x00 (II): SR07: 0x00 (II): MSR: 0x67 (II): ARX: 0x20 (II): AR00: 0x12 (II): AR01: 0x02 (II): AR02: 0x03 (II): AR03: 0x04 (II): AR04: 0x05 (II): AR05: 0x06 (II): AR06: 0x07 (II): AR07: 0x08 (II): AR08: 0x09 (II): AR09: 0x0a (II): AR0a: 0x0b (II): AR0b: 0x0c (II): AR0c: 0x11 (II): AR0d: 0x0e (II): AR0e: 0x0f (II): AR0f: 0x13 (II): AR10: 0x0c (II): AR11: 0x00 (II): AR12: 0x0f (II): AR13: 0x08 (II): AR14: 0x00 (II): CR00: 0x5f (II): CR01: 0x4f (II): CR02: 0x50 (II): CR03: 0x82 (II): CR04: 0x55 (II): CR05: 0x81 (II): CR06: 0xbf (II): CR07: 0x1f (II): CR08: 0x00 (II): CR09: 0x4f (II): CR0a: 0x0d (II): CR0b: 0x0e (II): CR0c: 0x0c (II): CR0d: 0x30 (II): CR0e: 0x13 (II): CR0f: 0xb0 (II): CR10: 0x9c (II): CR11: 0x0e (II): CR12: 0x8f (II): CR13: 0x28 (II): CR14: 0x1f (II): CR15: 0x96 (II): CR16: 0xb9 (II): CR17: 0xa3 (II): CR18: 0xff (II): CR19: 0x00 (II): CR1a: 0x00 (II): CR1b: 0x00 (II): CR1c: 0x00 (II): CR1d: 0x00 (II): CR1e: 0x00 (II): CR1f: 0x00 (II): CR20: 0x00 (II): CR21: 0x00 (II): CR22: 0x20 (II): CR23: 0x00 (II): CR24: 0x80 (II): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10 (II): pipe B dot 54166 n 2 m1 14 m2 9 p1 3 p2 14 (II): DumpRegsEnd
