On Friday, December 16, 2005 11:10 pm, David S. Miller wrote: > From: Jesse Barnes <[EMAIL PROTECTED]> > Date: Fri, 16 Dec 2005 16:41:49 -0800 > > > Note that under contention prefetching with a write bias can cause > > a lot more cache line bouncing than a regular load into shared > > state (assuming you do a load and test before you try the CAS). > > If there is some test guarding the CAS, yes.
Yeah, I was only referring to that particular case (the ia64 code does test then CAS, so removing the write bias on the load avoided a lot of thrashing for locks under contention). > But if there isn't, for things like atomic increment and > decrement, where the CAS is unconditional, you'll always > eat the two bus transactions without the prefetch for write. Right, in that case, biasing for read might make sense, as long as some other CPU doesn't cause the line to go back to shared before you actually get to the CAS. Jesse
