On Tuesday 07 March 2006 18:40, David Howells wrote: > +Older and less complex CPUs will perform memory accesses in exactly the order > +specified, so if one is given the following piece of code: > + > + a = *A; > + *B = b; > + c = *C; > + d = *D; > + *E = e; > + > +It can be guaranteed that it will complete the memory access for each > +instruction before moving on to the next line, leading to a definite sequence > +of operations on the bus:
Actually gcc is free to reorder it (often it will not when it cannot prove that they don't alias, but sometimes it can) > + > + Consider, for example, an ethernet chipset such as the AMD PCnet32. It > + presents to the CPU an "address register" and a bunch of "data > registers". > + The way it's accessed is to write the index of the internal register you > + want to access to the address register, and then read or write the > + appropriate data register to access the chip's internal register: > + > + *ADR = ctl_reg_3; > + reg = *DATA; You're not supposed to do it this way anyways. The official way to access MMIO space is using read/write[bwlq] Haven't read all of it sorry, but thanks for the work of documenting it. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
