Linus Torvalds <[EMAIL PROTECTED]> wrote: > Basically, as long as nobody else is reading the lock, the lock will stay > in the caches.
I think for the purposes of talking about memory barriers, we consider the cache to be part of the memory since the cache coherency mechanisms will give the same effect. I suppose the way the cache can be viewed as working is that bits of memory are shuttled around between the CPUs, RAM and any other devices that partake of the coherency mechanism. > All modern CPU's do atomic operations entirely within the cache coherency > logic. I know that, and I think it's irrelevant to specifying memory barriers. > I think x86 still support the notion of a "locked cycle" on the > bus, I wonder if that's what XCHG and XADD do... There's no particular reason they should be that much slower than LOCK INCL/DECL. Of course, I've only measured this on my Dual-PPro test box, so other i386 arch CPUs may exhibit other behaviour. David - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
