On Sun, 2006-03-19 at 13:25 -0800, David S. Miller wrote: > This is exactly what Sparc64's caches are too, L1 D-cache is virtually > indexed and physically tagged. But any bus coherency transaction will > update all lines with matching physical tags, otherwise things just > won't work.
I'm afraid ours don't. The reason is that parisc caches are huge (around a megabyte), so you have to specify a coherence index (which is effectively the virtual index) to the IOMMU on DMA transactions and that's the only line it flushes (as long as the physical tags match). > > OK, I confess to not ever having looked at that ... does it use > > get_user_pages() as well? > > I believe so, Andrew knows... OK I'll wait to see what he says. James - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
