Add platform data and base address for SDCC on QSD8x50. This adds support for slot 1, slot 2 and slot 3.
Signed-off-by: Sahitya Tummala <[email protected]> --- arch/arm/mach-msm/board-qsd8x50.c | 184 +++++++++++++++++++++- arch/arm/mach-msm/devices-qsd8x50.c | 196 +++++++++++++++++++++++ arch/arm/mach-msm/gpiomux-8x50.c | 107 ++++++++++++ arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 8 +- 4 files changed, 490 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 9e4cf24..7760ad0 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,6 +20,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/err.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -30,6 +31,8 @@ #include <mach/irqs.h> #include <mach/sirc.h> #include <mach/gpio.h> +#include <mach/vreg.h> +#include <mach/mmc.h> #include "devices.h" @@ -78,6 +81,182 @@ static struct platform_device *devices[] __initdata = { &msm_device_uart3, }; +#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) +struct sdcc_gpio_data { + unsigned no; + const char *name; +}; + +static struct sdcc_gpio_data sdc1_gpio_cfg[] = { + {51, "sdc1_dat_3"}, + {52, "sdc1_dat_2"}, + {53, "sdc1_dat_1"}, + {54, "sdc1_dat_0"}, + {55, "sdc1_cmd"}, + {56, "sdc1_clk"} +}; + +static struct sdcc_gpio_data sdc2_gpio_cfg[] = { + {62, "sdc2_clk"}, + {63, "sdc2_cmd"}, + {64, "sdc2_dat_3"}, + {65, "sdc2_dat_2"}, + {66, "sdc2_dat_1"}, + {67, "sdc2_dat_0"} +}; + +static struct sdcc_gpio_data sdc3_gpio_cfg[] = { + {88, "sdc3_clk"}, + {89, "sdc3_cmd"}, + {90, "sdc3_dat_3"}, + {91, "sdc3_dat_2"}, + {92, "sdc3_dat_1"}, + {93, "sdc3_dat_0"}, +}; + +struct msm_sdcc_gpio { + struct sdcc_gpio_data *cfg_data; + uint32_t size; + uint32_t cfg_sts; +}; + +static struct msm_sdcc_gpio sdcc_cfg_data[] = { + { + .cfg_data = sdc1_gpio_cfg, + .size = ARRAY_SIZE(sdc1_gpio_cfg), + }, + { + .cfg_data = sdc2_gpio_cfg, + .size = ARRAY_SIZE(sdc2_gpio_cfg), + }, + { + .cfg_data = sdc3_gpio_cfg, + .size = ARRAY_SIZE(sdc3_gpio_cfg), + }, + { + .cfg_data = NULL, + }, +}; + +static void msm_sdcc_setup_gpio(int dev_id, unsigned int enable) +{ + int rc = 0; + struct msm_sdcc_gpio *curr; + int n; + + curr = &sdcc_cfg_data[dev_id - 1]; + + if (!curr->cfg_data) { + pr_err("%s: gpio data is not defined for slot %d\n", + __func__, dev_id); + rc = -EINVAL; + goto out; + } + + if (curr->cfg_sts == enable) + goto out; + + for (n = 0; n < curr->size; n++) { + if (enable) { + rc = gpio_request(curr->cfg_data[n].no, + curr->cfg_data[n].name); + if (rc) { + pr_err("%s: gpio_request(%d, %s) failed %d\n", + __func__, curr->cfg_data[n].no, + curr->cfg_data[n].name, rc); + goto free_gpios; + } + /* set direction as output for all GPIOs */ + rc = gpio_direction_output(curr->cfg_data[n].no, 1); + if (rc) { + pr_err("%s: gpio_direction_output" + "(%d, 1) failed (%d)\n", __func__, + curr->cfg_data[n].no, rc); + goto free_gpios; + } + } else { + /* + * now free this GPIO which will put GPIO + * in low power mode and will also put GPIO + * in input mode + */ + gpio_free(curr->cfg_data[n].no); + } + } + curr->cfg_sts = enable; + goto out; + +free_gpios: + for (; n >= 0; n--) + gpio_free(curr->cfg_data[n].no); +out: + return; +} + +static struct vreg *vreg_mmc; +static unsigned long vreg_sts; + +static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd) +{ + int rc = 0; + struct platform_device *pdev; + + pdev = container_of(dv, struct platform_device, dev); + msm_sdcc_setup_gpio(pdev->id, !!vdd); + + if (vdd == 0) { + if (!vreg_sts) + return 0; + + clear_bit(pdev->id, &vreg_sts); + + if (!vreg_sts) { + rc = vreg_disable(vreg_mmc); + if (rc) + printk(KERN_ERR "%s: return val: %d\n", + __func__, rc); + } + return 0; + } + + if (!vreg_sts) { + rc = vreg_set_level(vreg_mmc, 2900); + if (!rc) + rc = vreg_enable(vreg_mmc); + if (rc) + printk(KERN_ERR "%s: return val: %d\n", + __func__, rc); + } + set_bit(pdev->id, &vreg_sts); + return 0; +} + +static struct msm_mmc_platform_data qsd8x50_sdcc_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .translate_vdd = msm_sdcc_setup_power, +}; + +static void __init qsd8x50_init_mmc(void) +{ + if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) + vreg_mmc = vreg_get(NULL, "gp6"); + else + vreg_mmc = vreg_get(NULL, "gp5"); + + if (IS_ERR(vreg_mmc)) { + printk(KERN_ERR "%s: vreg get failed (%ld)\n", + __func__, PTR_ERR(vreg_mmc)); + return; + } + + msm_add_sdcc(1, &qsd8x50_sdcc_data, 0, 0); + if (machine_is_qsd8x50_surf() || machine_is_qsd8x50a_surf()) { + msm_add_sdcc(2, &qsd8x50_sdcc_data, 0, 0); + msm_add_sdcc(3, &qsd8x50_sdcc_data, 0, 0); + } +} +#endif + static void __init qsd8x50_map_io(void) { msm_map_qsd8x50_io(); @@ -93,6 +272,9 @@ static void __init qsd8x50_init_irq(void) static void __init qsd8x50_init(void) { platform_add_devices(devices, ARRAY_SIZE(devices)); +#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) + qsd8x50_init_mmc(); +#endif } MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 4d4a507..61748db 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -48,6 +48,194 @@ struct platform_device msm_device_uart3 = { .resource = resources_uart3, }; +static struct resource resources_sdc1[] = { + { + .start = MSM_SDC1_PHYS, + .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC1_0, + .end = INT_SDC1_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC1_1, + .end = INT_SDC1_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc2[] = { + { + .start = MSM_SDC2_PHYS, + .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC2_0, + .end = INT_SDC2_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC2_1, + .end = INT_SDC2_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc3[] = { + { + .start = MSM_SDC3_PHYS, + .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC3_0, + .end = INT_SDC3_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC3_1, + .end = INT_SDC3_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc4[] = { + { + .start = MSM_SDC4_PHYS, + .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC4_0, + .end = INT_SDC4_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC4_1, + .end = INT_SDC4_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device msm_device_sdc1 = { + .name = "msm_sdcc", + .id = 1, + .num_resources = ARRAY_SIZE(resources_sdc1), + .resource = resources_sdc1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc2 = { + .name = "msm_sdcc", + .id = 2, + .num_resources = ARRAY_SIZE(resources_sdc2), + .resource = resources_sdc2, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc3 = { + .name = "msm_sdcc", + .id = 3, + .num_resources = ARRAY_SIZE(resources_sdc3), + .resource = resources_sdc3, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc4 = { + .name = "msm_sdcc", + .id = 4, + .num_resources = ARRAY_SIZE(resources_sdc4), + .resource = resources_sdc4, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *msm_sdcc_devices[] __initdata = { + &msm_device_sdc1, + &msm_device_sdc2, + &msm_device_sdc3, + &msm_device_sdc4, +}; + +int __init msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags) +{ + struct platform_device *pdev; + struct resource *res; + + if (controller < 1 || controller > 4) + return -EINVAL; + + pdev = msm_sdcc_devices[controller-1]; + pdev->dev.platform_data = plat; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); + if (!res) + return -EINVAL; + else if (stat_irq) { + res->start = res->end = stat_irq; + res->flags &= ~IORESOURCE_DISABLED; + res->flags |= stat_irq_flags; + } + + return platform_device_register(pdev); +} + struct clk msm_clocks_8x50[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), @@ -68,6 +256,14 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c index 4406e0f..1b7d15a 100644 --- a/arch/arm/mach-msm/gpiomux-8x50.c +++ b/arch/arm/mach-msm/gpiomux-8x50.c @@ -16,6 +16,23 @@ */ #include "gpiomux.h" +#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) + #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) + #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) +#else + #define SDCC_DAT_0_3_CMD_ACTV_CFG 0 + #define SDCC_CLK_ACTV_CFG 0 +#endif + +#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\ + | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) +#define SDC2_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\ + | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) +#define SDC3_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\ + | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) + struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { [86] = { /* UART3 RX */ .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | @@ -25,4 +42,94 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | GPIOMUX_FUNC_1 | GPIOMUX_VALID, }, + /* SDC1 data[3] */ + [51] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 data[2] */ + [52] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 data[1] */ + [53] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 data[0] */ + [54] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 CMD */ + [55] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 CLK */ + [56] = { + .active = SDCC_CLK_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC2 CLK */ + [62] = { + .active = SDCC_CLK_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC2 CMD */ + [63] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC2 data[3] */ + [64] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC2 data[2] */ + [65] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC2 data[1] */ + [66] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC2 data[0] */ + [67] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC2_SUSPEND_CONFIG + }, + /* SDC3 CLK */ + [88] = { + .active = SDCC_CLK_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, + /* SDC3 CMD */ + [89] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, + /* SDC3 data[3] */ + [90] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, + /* SDC3 data[2] */ + [91] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, + /* SDC3 data[1] */ + [92] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, + /* SDC3 data[0] */ + [93] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC3_SUSPEND_CONFIG + }, }; diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819e..732a965 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -132,16 +132,16 @@ #define MSM_UART2DM_PHYS 0xA0900000 -#define MSM_SDC1_PHYS 0xA0400000 +#define MSM_SDC1_PHYS 0xA0300000 #define MSM_SDC1_SIZE SZ_4K -#define MSM_SDC2_PHYS 0xA0500000 +#define MSM_SDC2_PHYS 0xA0400000 #define MSM_SDC2_SIZE SZ_4K -#define MSM_SDC3_PHYS 0xA0600000 +#define MSM_SDC3_PHYS 0xA0500000 #define MSM_SDC3_SIZE SZ_4K -#define MSM_SDC4_PHYS 0xA0700000 +#define MSM_SDC4_PHYS 0xA0600000 #define MSM_SDC4_SIZE SZ_4K #endif -- 1.7.1 -- Consultant for Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
