The driver explicitly requests a clock rate for the UART, but it is
off by a factor of four from the dividers that it programs into the
UART. Fix this by setting the rate to 1/4 of the current value.
Signed-off-by: David Brown <dav...@codeaurora.org>
---
drivers/tty/serial/msm_serial.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 29cbfd8..b7baceb 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -891,7 +891,7 @@ static int __init msm_serial_probe(struct platform_device
*pdev)
return PTR_ERR(msm_port->clk);
if (msm_port->is_uartdm)
- clk_set_rate(msm_port->clk, 7372800);
+ clk_set_rate(msm_port->clk, 1843200);
port->uartclk = clk_get_rate(msm_port->clk);
printk(KERN_INFO "uartclk = %d\n", port->uartclk);
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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