From: Srinivas Kandagatla <srinivas.kandaga...@linaro.org>
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have passed.
This patch adds a 3 clock cycle delay required after writing to controller
registers on Qualcomm SOCs. Without this delay all the register writes are not
successfull, resulting in not detecting cards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandaga...@linaro.org>
---
drivers/mmc/host/mmci.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4f8d0ba..f73dc48 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -179,6 +179,14 @@ static inline u32 mmci_readl(struct mmci_host *host, u32
off)
static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off)
{
writel(data, host->base + off);
+
+ /*
+ * On QCom SD card controller, registers must be updated to the
+ * MCLK domain so subsequent writes to this register will be ignored
+ * for 3 clk cycles.
+ */
+ if (host->hw_designer == AMBA_VENDOR_QCOM)
+ udelay(1 + ((3 * USEC_PER_SEC)/host->mclk));
}
static int mmci_card_busy(struct mmc_host *mmc)
--
1.7.9.5
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