[...]
> Moreover for burst mode to be enabled the MRS comamnd has to
> be given to the
> SDRAM . How to do this ? Or is it a fact that there is only
> burst of 1 in SA1110?
Actually you are right:
"10.3.4 SDRAM overview
[...]
Whenever an SDRAM bank is enabled, a mode register set (MSR)
command is sent to the SDRAM devices. MRS commands always
configure SDRAM internam mode registers for sequential burst type
and a burst length of one."
However, Figure 10-10 "SDRAM 8-Beat Read/Write Timing" clearly shows
something similar, where 8 words are read in sequence for each memory
clock beat. AFAIK, this is enabled automatically as soon as you turn
the cache on (!! it will NOT be used otherwise). So even if there are
bursts of one only, you still get the full bandwidth you can excpect
from the bus.
As to the difference between beats and bursts, I'll let you read from
your SDRAM datasheet (and tell me if you find out, I'm wondering now
and I can't find out :-)
Cheers,
Yves
_______________________________________________
http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm
Please visit the above address for information on this list.
