Hi Mr.Erik,

 Thanks a lot for your reply. It acted as an inspiration for us to work and
sort the issue. The issue was with Serial port and we have sorted it out.
Now blob is coming up to the level of "Starting Kernel...." 

One another problem we are facing is On "Blob>" we could not type any
command, We are using Windows 98 Hyper terminal. We are using settings as
gien in LART site "9600,8,N,1,VT100. Could you guide us.

Regards,
Abi

-----Original Message-----
From: Erik Mouw [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, January 16, 2002 8:30 PM
To: Abi Varghese M (OCS-BLRSJP-PEG)
Cc: ''
Subject: Re: Blob stalls with my design


On Wed, Jan 16, 2002 at 04:48:31PM +0530, Abi Varghese M (OCS-BLRSJP-PEG)
wrote:
>  I'm a hardware designer and is facing problem with my Intel StrongARM
based
> design and blob.
> 
>  Problem: 
> 
> blob 1.0.8 stalls after throwing the following text to the Serial port.:
> 
> Consider yourself LARTed!
> Starting the memory tester...
> Zeroing memory...0xC0000000

Memory zeroing should always proceed. Looks like a memory setup problem
but blob-1.0.8 did that wrong on SA-1110 anyway, so it doesn't help us
much.

> Blob 2.0.5 pre1 stalls after throwing the following text to the Serial
port:
> 
> Consider yourself LARTed!
> 
> blob version 2.0.5-pre2 for Intel Assabet

Good, you're using blob-2.0.5-pre2 cause that's much easier to port to
new architectures (the current CVS version can almost be ported to
non-StrongARM architectures).

> Copyright (C) 1999 2000 2001 Jan-Derk Bakker and Erik Mouw
> blob comes with ABSOLUTELY NO WARRANTY; read the GNU GPL for ?

Blob should print 'details.' as last word on the line. Do you really
get a '?' as the last word on the line? If so, it's another indication
that there is something wrong with your memory setup.

> I checked the source code and find that its the next function to run is
> get_memory_map().

If that function fails, it's a very strong indication that there really
is something wrong with the memory setup. Could you configure blob with
--enable-blob-debug and recompile it? It makes blob very verbose, but
it also prints what memory get_memory_map() discovers.

>  My memory design and implementation is very same as that
> of Intel Assabet board.

That doesn't give any information. All SA-1110 boards look like the
Assabet simply because all SA-1110 boards use an SA-1110 CPU. Just have
a look in include/blob/arch/ : there are already 6 other SA-1110 boards
that "look like Assabet" but they still need their own set of board
specific definitions.

> I checked the hardware signals and don't see any
> problem with Memory circuit and signals ( like clock,CAS , RAS Bank sel,
CE
> etc..  I request any of you to help me out.

I really think there is something wrong with the memory timing setup
for your board. You are currently using the Assabet memory timings, but
I bet that your board has different SDRAMs and hence needs different
timings. Just port your board to blob, it's really very easy (see
doc/porting.txt). In include/blob/arch/yourboard.h you'll have to fill
out the memory timings. You can do it by hand (there are macros for
that, just look at badge.h or system3.h), but you can also use Intel's
memory timing calculator at http://appzone.intel.com/hcd/sa1110/memory/ .

Another thing to check out is if you have anything connected to GPIO
17. The Assabet has a LED on that GPIO, but if your board uses it for
something else, weird things can happen. It's in the board specific
file again.

If that still doesn't solve the problem, it starts to look like a
hardware problem. In that case the best you can do is to ask somebody
who designed an SA-1110 board before to check the schematics and/or PCB
layout of your board.


Erik

-- 
J.A.K. (Erik) Mouw, Information and Communication Theory Group, Faculty
of Information Technology and Systems, Delft University of Technology,
PO BOX 5031, 2600 GA Delft, The Netherlands  Phone: +31-15-2783635
Fax: +31-15-2781843  Email: [EMAIL PROTECTED]
WWW: http://www-ict.its.tudelft.nl/~erik/




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