>with cache?). I did not stress enough: I am not surprised from the sequence
>of addresses (which is clearly affected by the pipeline) but the sequential
>memory access signal from the ARM after the data was loaded.
It could simply be a bug in the ARMulator. I can't find my ARM7 data sheet
right now so I'm not sure what the exact semantics for SEQ are supposed to
be (the SA110 has a slightly different, and essentially pretty useless,
meaning for this pin).
>> You are probably seeing a cache line fill and/or simple read ahead since
>> the Program Counter is ahead of the execute pipeline.
>>> 00008084 (Load Instruction - non-sequential cycle)
>>> 00008088 (Load Instruction - sequential cycle)
>>> 0000808C (Load Instruction - sequential cycle)
>>> 000080A3 (Load Byte - non - sequential cycle)
>>> 00008090 (Load Instruction - sequential cycle)
>>> 00008094 (Load Instruction - sequential cycle)
>>> 00008098 (Load Instruction - sequential cycle)
>>> 00008084 (Load Instruction - non-sequential cycle)
A cache fill would start at 0x8080 and run all the way up to 0x808c without
interruption. Also if the Icache was enabled the cpu wouldn't re-fetch the
loop instructions. So that doesn't look like it's what's happening.
p.
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