[EMAIL PROTECTED] said:
> So, if I read this right there should be no problem for any real-world
> situation. That's good.
Except your real-world argument was to claim an extra couple of cycles so
you can turn FIQs off.
I was in the process of doing the maths with all the latency issues, and
it really does not leave very much bandwidth for the FIQ operation and a
foreground operation running at the same time. I need to recheck the
calculations and extrapolations, since most of the figures are derived
from the data sheets for the original MEMC, VIDC and ARM (and check it
on the actual hardware).
--
Russell King ([EMAIL PROTECTED])
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