Philip Blundell writes:
> Command 0011 is an I/O write, and of course ISA I/O address 0x21 is the
> first PIC. Since IACK is a read cycle it almost certainly requires the
> outbound FIFO to be flushed.
Aha, as I was expecting...
> It's hard to say what happens in this case. From the description you've given
> of the control bit, I'd expect the lock-up to occur with the 21285 having bus
> ownership (because it sits waiting for a TRDY that never comes; the latency
> timer doesn't really protect you against this case).
I don't think the 21285 is at fault - it's looking like the Southbridge chip
isn't behaving as PCI 2.1 would expect. Ok, it's giving retries which are allowed,
but surely it should not block accesses while a DMA operation is in progress (since
you therefore cannot get to the DMA controller or device to stop it).
> It may well not have a latency timer if it's not capable of burst transfers.
> Even if it did, it wouldn't help in either of the failure modes you're seeing
> -- in the first one you described, the southbridge is correctly relinquishing
> the bus anyway, and in the second one the arbiter isn't removing its GNT so
> the latency timer would have no effect.
The arbiter is behaving as expected - in the total lock condition, the SA110 is
stalled while a memory read is processed. However, the 21285 doesn't have anything
to do on the PCI, so it's request is not activated. Therefore, the arbiter does
not remove the grant to the Southbridge since no other master is requesting the
bus.
> Does the documentation or errata for the southbridge say anything about the
> circumstances under which it responds with retry to target write transactions?
While looking for this, I suspect that the problems I'm seeing is why the chip
has gone obsolete about a year ago. Unfortunately, Cypress have cleaned their
web site of all obsolete erratas and data sheets.
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