On Wed, Oct 27, 1999, Francois Desloges <[EMAIL PROTECTED]> wrote:
>As I can easily program EBSA-285 Flash Bank 0. I wish to be able to run the
>Russell's BIOS 1.05 in this initial bank. The BIOS entry code look like this
>(the comments are from me) :
>
>> bic r11, lr, #3 @ r11 = LinkRegister & 0xFFFFFFFC;
>> mrs r0, cpsr @ Change to supervisor mode with IRQ
>and > bic r0, r0, #0x1f @ FIQ disabled
>> orr r0, r0, #0xd3
>> msr cpsr, r0
>> ldr sp, [r11, #8] @ StackPointer= *((LinkRegister & 0xFFFFFFFC)+8)
>
>I don't have PBL source code. What's 8 bytes after the bl to Bank #3?
>And is there another stack space I can use into the BIOS if I eliminate the
>PBL?
>Oh and why clear the last two bits of lr, doesn't ARM alignment force them at
>0 anyway?
At this point of boot, there is no stack (and possibly no RAM).
r11 contains the link (aligned) and in sp is stored the value at 8(r11).
This is because the BIOS entry expects to be called by the AIF header's
code which does basically a "bl entry". This header contains, after this
bl, a field with the size of the data section (stored here by mkaif).
This size is stored in sp and is used later, after the RAM detection,
when copying the datas to RAM.
I beleive this could be improved by using linker tricks to have the
linker store this size in a place where the code can fetch it via
pc-relative access, but I don't know ld well enough to write such a script.
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