>>>>> "VR" == Vasant Ramasubramanian <[EMAIL PROTECTED]> writes:
VR> I've spent the last few days trying very hard to get the SDRAM
VR> working on a custom SA1110 based board but have failed thus far.
VR> Does anyone (besides blob & Compaq/bootldr) have simple assembly
VR> code to "wake-up" the SDRAMs(follow through the state machine
VR> listed in the 1110 manual) and configure & enable them?
VR> At this point I am unable to read/write to SDRAM after trying my
VR> code; I do all my initalization after RESET so the MMU is
VR> unconfigured and caches are turned off.
[snip]
There are some problems with the SA1110 SDRAM controller. It only
works at some speeds. I think that with a 1/4 speed bus, it will
always work. However, using the 1/2 speed bus, it will work from
187-200Mhz and from 50-118Mhz depending on the CAS latency. I don't
think this is mentioned in errata (or whatever they call it).
Unfortunately, the SA1110 SDRAM controller doesn't give you control
over the waveforms like say the UPM on an MPC860. This means that you
have to work with the parameters that the SA1110 provides.
Most SDRAM has the same state machine and commands. These are sent by
three control lines (I forget which), so there are eight different
commands (maybe more, one is an escape). Here are some 1/4 speed
numbers.
[start]
ppcr_speed:
.long 0x00000006 /* 147 Mhz */
mdcas00:
.long 0xaaaaaa7f /* 1/4 speed */
mdrefr0:
.long 0x00700321 /* 1/4 speed */
mdcas01:
.long 0xaaaaaaaa
mdcas02:
.long 0xaaaaaaaa
mdcnfg:
.long 0x72547254
initSDRAM:
ldr r0,memCfgAddr
ldr r1,mdcas00 /* MDCAS00 value. */
str r1,[r0,#0x4]
ldr r1,mdcas01 /* MDCAS01 value. */
str r1,[r0,#0x8]
ldr r1,mdcas02 /* MDCAS02 value. */
str r1,[r0,#0xc]
ldr r1,mdrefr0 /* MDREFR value. */
STR r1,[r0,#0x1c]
ldr r1,mdcnfg /* turn on the DRAM */
STR r1,[r0]
ldr r0,powCfgAddr
mov r1,#0x08 /* clear the DRAM Hold bit */
STR r1,[r0,#0x4]
/* Perform 8 reads from unenabled DRAM */
mov r1, #DRAM_PHYSICAL
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r0,memCfgAddr
ldr r1,mdcnfg /* enable the DRAM */
orr r1,r1,#1
STR r1,[r0]
/*
* Wait for DRAM to come up.
*/
MOV r1, #0x200
0: SUBS r1, r1, #1
BNE 0b
mov pc,lr /* return to caller. */
[end]
If 1/4 speed doesn't work, take a look at the hardware. If you are
lucky enough to have the bus broken out, hook up a logic analyzer and
take a look. Intel suggested added line traces/delay elements to get
things working at 1/2 speed. If you have a large trace, then things
might not work exactly like the Assabet, etc boards. This sucks and
is frustrating to debug...
hth,
Bill
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