>> In reading the documentation for the FPU on the Athlon,
>> they state that it can perform two pipelined double precision floating
>> point multiplies per cycle.

>Are we talking about SIMD instructions here? I've never used them, but
>with generic i686 as produced by gcc -O6:

My mistake.  It's one per cycle:  

http://www.amd.com/products/cpg/athlon/pdf/fpu_wp.pdf

I think that this is just raw FP performance; AMD states that only the MMX
and 3DNOW instructions are SIMD.

Another interesting document from AMD:

http://www.amd.com/products/cpg/athlon/techdocs/pdf/22007.pdf

Greg Berchin

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