On Mon, 07 Oct 2024 18:16:14 -0500
ira.we...@intel.com wrote:

> From: Navneet Singh <navneet.si...@intel.com>
> 
> Devices which optionally support Dynamic Capacity (DC) are configured
> via mailbox commands.  CXL 3.1 requires the host to issue the Get DC
> Configuration command in order to properly configure DCDs.  Without the
> Get DC Configuration command DCD can't be supported.
> 
> Implement the DC mailbox commands as specified in CXL 3.1 section
> 8.2.9.9.9 (opcodes 48XXh) to read and store the DCD configuration
> information.  Disable DCD if DCD is not supported.  Leverage the Get DC
> Configuration command supported bit to indicate if DCD support.
> 
> Linux has no use for the trailing fields of the Get Dynamic Capacity
> Configuration Output Payload (Total number of supported extents, number
> of available extents, total number of supported tags, and number of
> available tags). Avoid defining those fields to use the more useful
> dynamic C array.
> 
> Cc: "Li, Ming" <ming4...@intel.com>
> Signed-off-by: Navneet Singh <navneet.si...@intel.com>
> Co-developed-by: Ira Weiny <ira.we...@intel.com>
> Signed-off-by: Ira Weiny <ira.we...@intel.com>

Looks fine to me.  Trivial comment inline
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>



> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index e8907c403edb..0690b917b1e0 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
...

> +/* See CXL 3.1 Table 8-164 get dynamic capacity config Output Payload */
> +struct cxl_mbox_get_dc_config_out {
> +     u8 avail_region_count;
> +     u8 regions_returned;
> +     u8 rsvd[6];
> +     /* See CXL 3.1 Table 8-165 */
> +     struct cxl_dc_region_config {
> +             __le64 region_base;
> +             __le64 region_decode_length;
> +             __le64 region_length;
> +             __le64 region_block_size;
> +             __le32 region_dsmad_handle;
> +             u8 flags;
> +             u8 rsvd[3];
> +     } __packed region[];

Could throw in a __counted_by I think?

> +     /* Trailing fields unused */
> +} __packed;
> +#define CXL_DYNAMIC_CAPACITY_SANITIZE_ON_RELEASE_FLAG BIT(0)
> +#define CXL_DCD_BLOCK_LINE_SIZE 0x40

Reply via email to