Hi Magnus,
On Tue, Sep 1, 2015 at 12:59 PM, Magnus Damm <[email protected]> wrote:
>>> +/*
>>> + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
>>> + * 14 13 19 17 (MHz) *1 *1 *1
>>> + *-------------------------------------------------------------------
>>> + * 0 0 0 0 16.66 x 1 x180/2 x192/2 x144/2 x192 x144
>>> + * 0 0 0 1 16.66 x 1 x180/2 x192/2 x144/2 x128 x144
>>> + * 0 0 1 0 Prohibited setting
>>> + * 0 0 1 1 16.66 x 1 x180/2 x192/2 x144/2 x192 x144
>>> + * 0 1 0 0 20 x 1 x150/2 x156/2 x120/2 x156 x120
>>> + * 0 1 0 1 20 x 1 x150/2 x156/2 x120/2 x106 x120
>>> + * 0 1 1 0 Prohibited setting
>>> + * 0 1 1 1 20 x 1 x150/2 x156/2 x120/2 x156 x120
>>> + * 1 0 0 0 25 x 1 x120/2 x128/2 x96/2 x128 x96
>>> + * 1 0 0 1 25 x 1 x120/2 x128/2 x96/2 x84 x96
>>> + * 1 0 1 0 Prohibited setting
>>> + * 1 0 1 1 25 x 1 x120/2 x128/2 x96/2 x128 x96
>>> + * 1 1 0 0 33.33 / 2 x180/2 x192/2 x144/2 x192 x144
>>> + * 1 1 0 1 33.33 / 2 x180/2 x192/2 x144/2 x128 x144
>>> + * 1 1 1 0 Prohibited setting
>>> + * 1 1 1 1 33.33 / 2 x180/2 x192/2 x144/2 x192 x144
>>> + *
>>> + * *1 : datasheet indicates VCO output (PLLx = VCO/2)
>>
>> As explained in a separate e-mail there's a few clocks on R8A7795 that derive
>> directly from PLL1 VCO. I thus wonder whether we shouldn't expose the PLL1
>> clock as the VCO output and create VCO/2 using a fixed factor clock in DT.
>
> Do you think that would reduce complexity or simplify the code? If so
> I think we should do it. Otherwise I think it makes sense to simply
> follow the data sheet.
It would avoid having to apply a multiplier of two to the RPC clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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