On 08/27, Stephen Boyd wrote: > Sometimes the display driver may want to change the parent PLL of > the display clocks (byte and pixel clocks) depending on the > use-case. Currently the parent is fixed by means of having a > frequency table with one entry that chooses a particular parent. > Remove this restriction and use the parent the clock is > configured for in the hardware during clk_set_rate(). This > requires consumers to rely on the default parent or to configure > the parent with clk_set_parent()/assigned-clock-parents on the > clocks before calling clk_set_rate(). > > Cc: Archit Taneja <[email protected]> > Cc: Hai Li <[email protected]> > Signed-off-by: Stephen Boyd <[email protected]> > ---
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