On 3/4/24 13:27, Jarkko Sakkinen wrote:
> Based recent discussions on LKML, provide preliminary bits of tpm_tis_core
> dependent drivers. Includes only bare essentials but can be extended later
> on case by case. This way some people may even want to read it later on.
>
> Cc: Jonathan Corbet <[email protected]>
> CC: Daniel P. Smith <[email protected]>
> Cc: Lino Sanfilippo <[email protected]>
> Cc: Jason Gunthorpe <[email protected]>
> Cc: Peter Huewe <[email protected]>
> Cc: James Bottomley <[email protected]>
> Cc: Alexander Steffen <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Jarkko Sakkinen <[email protected]>
> ---
> Documentation/security/tpm/index.rst | 1 +
> Documentation/security/tpm/tpm_tis.rst | 30 ++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
> create mode 100644 Documentation/security/tpm/tpm_tis.rst
>
> diff --git a/Documentation/security/tpm/tpm_tis.rst
> b/Documentation/security/tpm/tpm_tis.rst
> new file mode 100644
> index 000000000000..3cec0216a169
> --- /dev/null
> +++ b/Documentation/security/tpm/tpm_tis.rst
> @@ -0,0 +1,30 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +=========================
> +TPM FIFO interface Driver
> +=========================
> +
> +FIFO (First-In-First-Out) is the name of the hardware interface used by the
> +`tpm_tis_core` dependent drivers. The prefix "tis" is named after TPM
> +Interface Specification, which is the hardware interface specification for
> +TPM 1.x chips.
> +
> +Communication is based on a 5 KiB buffer shared by the TPM chip through a
> +hardware bus or memory map. The buffer is further split to five equal size
> +buffers, which provide equivalent sets of registers for communication
> +between CPU and TPM. The communication end points are called *localities*
> +in the TCG terminology.
> +
> +When a kernel wants to send a commands to the TPM chip, it first reserves
> +locality 0 by setting `requestUse` bit in `TPM_ACCESS` register. The bit is
> +cleared by the chip when the access is granted. Once completed its
> +communication, it sets `activeLocity` bit in the same register.
Is that activeLocality ?
> +
> +Pending localities are served in order by the chip descending orderm and
> +one at a time:
> +
> +- Locality 0 has the lowest priority.
> +- Locality 5 has the highest priotiy.
priority.
> +
> +Further information on purpose and meaning of the localities can be found
> +from section 3.2 of TCG PC Client Platform TPM Profile Specification.
--
#Randy
