On Fri, May 23, 2025 at 07:55:18AM +0000, Tian, Kevin wrote:
> > From: Nicolin Chen <nicol...@nvidia.com>
> > Sent: Sunday, May 18, 2025 11:22 AM
> >
> > +
> > +enum iommufd_viommu_flags {
> > + /*
> > + * The HW does not go through an address translation table but
> > reads the
> > + * physical address space directly: iommufd core should pin the
> > physical
> > + * pages backing the queue memory that's allocated for the HW
> > QUEUE, and
> > + * ensure those physical pages are contiguous in the physical space.
> > + */
> > + IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA = 1 << 0,
> > +};
>
> The queue itself doesn't read an address.
>
> What about 'QUEUE_BASE_PA'?
But the HW queue object represents the HW feature, not the guest
queue memory. So, it is accurate to say that it reads an address?
We have this in doc:
- IOMMUFD_OBJ_HW_QUEUE, representing a hardware accelerated queue, as a subset
of IOMMU's virtualization features, for the IOMMU HW to directly read or write
the virtual queue memory owned by a guest OS. This HW-acceleration feature can
...
Thanks
Nic
