Re: [PATCH v2 01/23] arm64: cpufeature: Add cpucap for HPMN0

[Colton Lewis]

Oliver Upton <oliver.up...@linux.dev> writes:

On Fri, Jun 20, 2025 at 10:13:01PM +0000, Colton Lewis wrote:

Add a capability for FEAT_HPMN0, whether MDCR_EL2.HPMN can specify 0
counters reserved for the guest.

This required changing HPMN0 to an UnsignedEnum in tools/sysreg
because otherwise not all the appropriate macros are generated to add
it to arm64_cpu_capabilities_arm64_features.

Signed-off-by: Colton Lewis <coltonle...@google.com>
---
  arch/arm64/kernel/cpufeature.c | 8 ++++++++
  arch/arm64/tools/cpucaps       | 1 +
  arch/arm64/tools/sysreg        | 6 +++---
  3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c

index b34044e20128..278294fdc97d 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -548,6 +548,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
  };

  static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {

+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), @@ -2896,6 +2897,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {

                .matches = has_cpuid_feature,
                ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2)
        },
+       {
+               .desc = "Allow MDCR_EL2.HPMN = 0",

This feedback still stands...

                .desc = "HPMN0",

[*] https://lore.kernel.org/kvm/ad4ijuasgm9b2...@linux.dev/

Sorry for ignoring your previous feedback. I looked at the other .desc
fields and they had more descriptive English, so I think this one should
be more than "FEAT_HPMN0" for consistency.

If you insist I'll change it.

+               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+               .capability = ARM64_HAS_HPMN0,
+               .matches = has_cpuid_feature,
+               ARM64_CPUID_FIELDS(ID_AA64DFR0_EL1, HPMN0, IMP)
+       },
  #ifdef CONFIG_ARM64_SME
        {
                .desc = "Scalable Matrix Extension",

Here's one example.

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 10effd4cff6b..5b196ba21629 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -39,6 +39,7 @@ HAS_GIC_CPUIF_SYSREGS
  HAS_GIC_PRIO_MASKING
  HAS_GIC_PRIO_RELAXED_SYNC
  HAS_HCR_NV1
+HAS_HPMN0
  HAS_HCX
  HAS_LDAPR
  HAS_LPA2
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8a8cf6874298..d29742481754 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1531,9 +1531,9 @@ EndEnum
  EndSysreg

  Sysreg        ID_AA64DFR0_EL1 3       0       0       5       0
-Enum   63:60   HPMN0
-       0b0000  UNPREDICTABLE
-       0b0001  DEF
+UnsignedEnum   63:60   HPMN0
+       0b0000  NI
+       0b0001  IMP
  EndEnum
  UnsignedEnum  59:56   ExtTrcBuff
        0b0000  NI
--
2.50.0.714.g196bf9f422-goog