Re: [PATCH v3 01/22] arm64: cpufeature: Add cpucap for HPMN0

[Colton Lewis]

Mark Rutland <mark.rutl...@arm.com> writes:

On Thu, Jun 26, 2025 at 08:04:37PM +0000, Colton Lewis wrote:

Add a capability for FEAT_HPMN0, whether MDCR_EL2.HPMN can specify 0
counters reserved for the guest.

This required changing HPMN0 to an UnsignedEnum in tools/sysreg
because otherwise not all the appropriate macros are generated to add
it to arm64_cpu_capabilities_arm64_features.

I agree it's appropriate to mark ID_AA64DFR0_EL1.HPMN0 as an
UnsignedEnum. It follows the usual ID scheme per ARM DDI 0487 L.a
section D24.1.3, and zero means not present, so it must be unsigned.

Likewise, the value renames (UNPREDICTABLE => NI and DEF => IMP) look
fine to me.

Signed-off-by: Colton Lewis <coltonle...@google.com>

I have one minor nit below, but either way:

Acked-by: Mark Rutland <mark.rutl...@arm.com>

Thank you Mark

---
  arch/arm64/kernel/cpufeature.c | 8 ++++++++
  arch/arm64/tools/cpucaps       | 1 +
  arch/arm64/tools/sysreg        | 6 +++---
  3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c

index b34044e20128..73a7dac4b6f6 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -548,6 +548,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
  };

  static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {

+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), @@ -2896,6 +2897,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {

                .matches = has_cpuid_feature,
                ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2)
        },
+       {
+               .desc = "FEAT_HPMN0",

Minor nit, but we can drop the "FEAT_" prefix here, for consistency with
other features (e.g. E0PD, FPMR).

Mark.

Will do.

+               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+               .capability = ARM64_HAS_HPMN0,
+               .matches = has_cpuid_feature,
+               ARM64_CPUID_FIELDS(ID_AA64DFR0_EL1, HPMN0, IMP)
+       },
  #ifdef CONFIG_ARM64_SME
        {
                .desc = "Scalable Matrix Extension",
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 10effd4cff6b..5b196ba21629 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -39,6 +39,7 @@ HAS_GIC_CPUIF_SYSREGS
  HAS_GIC_PRIO_MASKING
  HAS_GIC_PRIO_RELAXED_SYNC
  HAS_HCR_NV1
+HAS_HPMN0
  HAS_HCX
  HAS_LDAPR
  HAS_LPA2
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8a8cf6874298..d29742481754 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1531,9 +1531,9 @@ EndEnum
  EndSysreg

  Sysreg        ID_AA64DFR0_EL1 3       0       0       5       0
-Enum   63:60   HPMN0
-       0b0000  UNPREDICTABLE
-       0b0001  DEF
+UnsignedEnum   63:60   HPMN0
+       0b0000  NI
+       0b0001  IMP
  EndEnum
  UnsignedEnum  59:56   ExtTrcBuff
        0b0000  NI
--
2.50.0.727.gbf7dc18ff4-goog