[PATCH v7 29/29] KVM: arm64: selftests: Add SME to set_id_regs test

[Mark Brown]

Add coverage of the SME ID registers to set_id_regs, ID_AA64PFR1_EL1.SME
becomes writable and we add ID_AA64SMFR_EL1 and it's subfields.

Signed-off-by: Mark Brown <broo...@kernel.org>
---
 tools/testing/selftests/kvm/arm64/set_id_regs.c | 27 ++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c 
b/tools/testing/selftests/kvm/arm64/set_id_regs.c
index d3bf9204409c..f3f15145aa69 100644
--- a/tools/testing/selftests/kvm/arm64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c
@@ -196,6 +196,28 @@ static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = {
        REG_FTR_END,
 };
 
+static const struct reg_ftr_bits ftr_id_aa64smfr0_el1[] = {
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, FA64, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, LUTv2, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SMEver, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I64, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F64F64, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16B16, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F16, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F16, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I8I32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16F32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, BI32I32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F32F32, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8FMA, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP4, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP2, 0),
+       REG_FTR_END,
+};
+
 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
        REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
        REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
@@ -227,6 +249,7 @@ static struct test_feature_reg test_regs[] = {
        TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
        TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
        TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1),
+       TEST_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0_el1),
        TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
 };
 
@@ -243,6 +266,7 @@ static void guest_code(void)
        GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
        GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
        GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
+       GUEST_REG_SYNC(SYS_ID_AA64SMFR0_EL1);
        GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
        GUEST_REG_SYNC(SYS_CTR_EL0);
        GUEST_REG_SYNC(SYS_MIDR_EL1);
@@ -784,7 +808,8 @@ int main(void)
                   ARRAY_SIZE(ftr_id_aa64isar2_el1) + 
ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
                   ARRAY_SIZE(ftr_id_aa64pfr1_el1) + 
ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
                   ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + 
ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
-                  ARRAY_SIZE(ftr_id_aa64mmfr3_el1) + 
ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
+                  ARRAY_SIZE(ftr_id_aa64mmfr3_el1) + 
ARRAY_SIZE(ftr_id_aa64smfr0_el1) +
+                  ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
                   ARRAY_SIZE(test_regs) + 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST;
 
        ksft_set_plan(test_cnt);

-- 
2.39.5