GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add
these to those validated by get-reg-list.

Reviewed-by: Thiago Jung Bauermann <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
---
 tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c 
b/tools/testing/selftests/kvm/arm64/get-reg-list.c
index 011fad95dd02..9bf33064377b 100644
--- a/tools/testing/selftests/kvm/arm64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c
@@ -42,6 +42,12 @@ struct feature_id_reg {
 static struct feature_id_reg feat_id_regs[] = {
        REG_FEAT(TCR2_EL1,      ID_AA64MMFR3_EL1, TCRX, IMP),
        REG_FEAT(TCR2_EL2,      ID_AA64MMFR3_EL1, TCRX, IMP),
+       REG_FEAT(GCSPR_EL0,     ID_AA64PFR1_EL1, GCS, IMP),
+       REG_FEAT(GCSPR_EL1,     ID_AA64PFR1_EL1, GCS, IMP),
+       REG_FEAT(GCSPR_EL2,     ID_AA64PFR1_EL1, GCS, IMP),
+       REG_FEAT(GCSCRE0_EL1,   ID_AA64PFR1_EL1, GCS, IMP),
+       REG_FEAT(GCSCR_EL1,     ID_AA64PFR1_EL1, GCS, IMP),
+       REG_FEAT(GCSCR_EL2,     ID_AA64PFR1_EL1, GCS, IMP),
        REG_FEAT(PIRE0_EL1,     ID_AA64MMFR3_EL1, S1PIE, IMP),
        REG_FEAT(PIRE0_EL2,     ID_AA64MMFR3_EL1, S1PIE, IMP),
        REG_FEAT(PIR_EL1,       ID_AA64MMFR3_EL1, S1PIE, IMP),
@@ -486,6 +492,9 @@ static __u64 base_regs[] = {
        ARM64_SYS_REG(3, 0, 2, 0, 1),   /* TTBR1_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 2),   /* TCR_EL1 */
        ARM64_SYS_REG(3, 0, 2, 0, 3),   /* TCR2_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 0),   /* GCSCR_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 1),   /* GCSPR_EL1 */
+       ARM64_SYS_REG(3, 0, 2, 5, 2),   /* GCSCRE0_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 0),   /* AFSR0_EL1 */
        ARM64_SYS_REG(3, 0, 5, 1, 1),   /* AFSR1_EL1 */
        ARM64_SYS_REG(3, 0, 5, 2, 0),   /* ESR_EL1 */
@@ -502,6 +511,7 @@ static __u64 base_regs[] = {
        ARM64_SYS_REG(3, 0, 13, 0, 4),  /* TPIDR_EL1 */
        ARM64_SYS_REG(3, 0, 14, 1, 0),  /* CNTKCTL_EL1 */
        ARM64_SYS_REG(3, 2, 0, 0, 0),   /* CSSELR_EL1 */
+       ARM64_SYS_REG(3, 3, 2, 5, 1),   /* GCSPR_EL0 */
        ARM64_SYS_REG(3, 3, 10, 2, 4),  /* POR_EL0 */
        ARM64_SYS_REG(3, 3, 13, 0, 2),  /* TPIDR_EL0 */
        ARM64_SYS_REG(3, 3, 13, 0, 3),  /* TPIDRRO_EL0 */
@@ -740,6 +750,8 @@ static __u64 el2_regs[] = {
        SYS_REG(PIRE0_EL2),
        SYS_REG(PIR_EL2),
        SYS_REG(POR_EL2),
+       SYS_REG(GCSPR_EL2),
+       SYS_REG(GCSCR_EL2),
        SYS_REG(AMAIR_EL2),
        SYS_REG(VBAR_EL2),
        SYS_REG(CONTEXTIDR_EL2),

-- 
2.47.2


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