On Tue, 23 Dec 2025 at 01:23, Mark Brown <[email protected]> wrote: > > With support for context switching SME state in place allow access to SME > in nested guests. > > The SME floating point state is handled along with all the other floating > point state, SME specific floating point exceptions are directed into the > same handlers as other floating point exceptions with NV specific handling > for the vector lengths already in place. > > TPIDR2_EL0 is context switched along with the other TPIDRs as part of the > main guest register context switch. > > SME priority support is currently masked from all guests including nested > ones. > > Signed-off-by: Mark Brown <[email protected]> > --- > arch/arm64/kvm/nested.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c > index cdeeb8f09e72..a0967ca8c61e 100644 > --- a/arch/arm64/kvm/nested.c > +++ b/arch/arm64/kvm/nested.c > @@ -1534,14 +1534,13 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) > break; > > case SYS_ID_AA64PFR1_EL1: > - /* Only support BTI, SSBS, CSV2_frac */ > + /* Only support BTI, SME, SSBS, CSV2_frac */ > val &= ~(ID_AA64PFR1_EL1_PFAR | > ID_AA64PFR1_EL1_MTEX | > ID_AA64PFR1_EL1_THE | > ID_AA64PFR1_EL1_GCS | > ID_AA64PFR1_EL1_MTE_frac | > ID_AA64PFR1_EL1_NMI | > - ID_AA64PFR1_EL1_SME |
Should we also limit this to SME2, i.e. + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR1_EL1, SME, SME2); That said, we don't do anything similar to SVE, but it might also be worth doing that there. Reviewed-by: Fuad Tabba <[email protected]> Cheers, /fuad > ID_AA64PFR1_EL1_RES0 | > ID_AA64PFR1_EL1_MPAM_frac | > ID_AA64PFR1_EL1_MTE); > > -- > 2.47.3 >
