Because the Partitioned PMU must lean heavily on underlying hardware support, it can't guarantee an exception occurs when accessing an invalid pmc index.
The ARM manual specifies that accessing PMEVCNTR<n>_EL0 where n is greater than the number of counters on the system is constrained unpredictable when FEAT_FGT is not implemented, and it is desired the Partitioned PMU still work without FEAT_FGT. Though KVM could enforce exceptions here since all PMU accesses without FEAT_FGT are trapped, that creates further difficulties. For one example, the manual also says that after writing a value to PMSELR_EL0 greater than the number of counters on a system, direct reads will return an unknown value, meaning KVM could not rely on the hardware register to hold the correct value. Signed-off-by: Colton Lewis <[email protected]> --- .../selftests/kvm/arm64/vpmu_counter_access.c | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c index 9702f1d43b832..27b7d7b2a059a 100644 --- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c @@ -38,10 +38,14 @@ const char *pmu_impl_str[] = { struct vpmu_vm { struct kvm_vm *vm; struct kvm_vcpu *vcpu; +}; + +struct guest_context { bool pmu_partitioned; }; static struct vpmu_vm vpmu_vm; +static struct guest_context guest_context; struct pmreg_sets { uint64_t set_reg_id; @@ -342,11 +346,16 @@ static void test_access_invalid_pmc_regs(struct pmc_accessor *acc, int pmc_idx) /* * Reading/writing the event count/type registers should cause * an UNDEFINED exception. + * + * If the pmu is partitioned, we can't guarantee it because + * hardware doesn't. */ - TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_cntr(pmc_idx)); - TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_cntr(pmc_idx, 0)); - TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_typer(pmc_idx)); - TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_typer(pmc_idx, 0)); + if (!guest_context.pmu_partitioned) { + TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_cntr(pmc_idx)); + TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_cntr(pmc_idx, 0)); + TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_typer(pmc_idx)); + TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_typer(pmc_idx, 0)); + } /* * The bit corresponding to the (unimplemented) counter in * {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers should be RAZ. @@ -459,7 +468,7 @@ static void create_vpmu_vm(void *guest_code, enum pmu_impl impl) vpmu_vm.vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, KVM_ARM_VCPU_PMU_V3_ENABLE_PARTITION); if (!ret) { vcpu_ioctl(vpmu_vm.vcpu, KVM_SET_DEVICE_ATTR, &part_attr); - vpmu_vm.pmu_partitioned = partition; + guest_context.pmu_partitioned = partition; pr_debug("Set PMU partitioning: %d\n", partition); } @@ -511,6 +520,7 @@ static void test_create_vpmu_vm_with_nr_counters( TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret)); vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PMU_V3_CTRL, KVM_ARM_VCPU_PMU_V3_INIT, NULL); + sync_global_to_guest(vpmu_vm.vm, guest_context); } /* -- 2.53.0.rc2.204.g2597b5adb4-goog
