here just a short outline how the firmware is supposed to work:
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in order to start a transaction the onchip 8051 does something like this
- initializes the transaction count register = 188
- start the GPIF state machine, state 1
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GPIF state 1
- wait until pin RDY0 (signal TSSYNC) goes high + INTRDY
(sync byte 0x47 is received and we have space in the FIFO)
- go to state 2
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GPIF state 2
- wait for RDY1 (signal TSCLK) going low
- go to state 3
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GPIF state 3
- wait for RDY1 (signal TSCLK) going high
- sample current data byte, write it into FIFO
- if transaction count > 0 go to state 2, elso go idle
and throw done_irq
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on done_irq the 8051 can take a look on the PID bytes in the packets:
- look up in the PID table if we're interested in this PID
- if so: pass this packet to the host PC, else skip this packet
- swap FIFO pages
- start transaction again
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