Hi!
See below.
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On 11/29/2003 at 5:30 AM Holger Waechtler wrote:
...
>>
>> In case you haven't yet tried: Doesn't work. Augusto seems to suggest,
>> that the high bits of the 0x3fff PID mask _must_ be cleared (this
>> explains the strange bit masks used sometimes in the code).
>
>MPEG-TS PIDs have 13 bits, thus 0x1fff is the correct mask everywhere.
>
>Holger
I think this is generating some confusion. I'll try to clarify the specifics for the
FC.
As we know, the transfer to the FC chips is done using 32-bits. We must provide all 32
bits. When writing to a PID register, the PID value has to be mask with 0x1fff.
There are three mass produced version of the Flexcop chip. They do share a lot of
registers, but the biggest difference is the number of PIDS. In a nutshell:
-FCII
6 HW PIDs + 1 Group PID
HW DEMUX and section filter. (3X)
-FCIIB
6 HW PIDs + 1 Group PID
Plus
32 HW PIDs
HW DEMUX (same as FCII) and section filter. (35X)
-FCIII
6 HW PIDs + 1 Group PID
Plus
32 HW PIDs
HW DEMUX(better than FCII) and section filter. (35X)
USB+PHY
Programmable RISC core
Note that these chips also have a smartcard controller built-in and FCIII has a
programmable CI interface.
The 6 HW filters are used as follows: (Applies to all FC versions including FPGA
versions and FCI)
0x300, 0x304, 0x308
Bits 12-0 PID value
Bit 13 Enable the internal demux for this PID. (Must be set to 0 for skystar2.c)
Bit 14 Enable Multicast for this PID. (Must be set to 0 for skystar2.c). This used to
filter only Multicast data after internally demux.
Bit 15 Reserved. (Debug/status on FCIII)
Bits 28-16 PID value
Bit 29 Same as 13
Bit 30 Same as 14
Bit 31 Same as 15
0x30c
Bits 12-0 PID value
Bit 13 Enable the internal demux for this PID. (Must be set to 0 for skystar2.c)
Bits 14-15 Reserved. (Debug/status on FCIII)
Bits 28-16 PID_mask value. Operation is ((Incoming PID) & PID_MASK) == PID value)
Bits 29-31 Reserved. (debug/status on FCIII)
0x208 This is the most important register in the FC
Bit 0 Enable PID 12-0 on 0x300
Bit 1 Enable PID 28-16 on 0x300
Bit 2 Enable PID 12-0 on 0x304
Bit 3 Enable PID 28-16 on 0x304
Bit 4 Enable PID 12-0 on 0x308
Bit 5 Enable PID 28-16 on 0x308
Bit 6 NULL Packets filter. When set or '1', filters out the 0x1fff packets.
Bit 7 Enables PID on 0x30c
Bit 8 Enables WAN port output. (Built-in HDLC port).
Bit 9-10 Internal CA enables. (FCII and FCIIB have a built-in embedded CA
engine system, not in use in Europe). Reserved in FCIII.
Bit 11 Enable smartcard interface.
Bit 12 Switches between the two external transport inputs on FCII and FCIIB. Reserved
on FCIII.
Bit 13 Reserved.
Bit 14 Enable section filter. Internal Demux only.
Bit 15 Enable data receiving. Should be set to '1' to receive data.
Bit 16 Enable DMA1 counter IRQ
Bit 17 Enable DMA1 timer IRQ
Bit 18 Enable DMA2 counter IRQ
Bit 19 Enable DMA2 timer IRQ
Bit 20 Enable DMA1 size IRQ. FCIII only.
Bit 21 Enable DMA2 size IRQ. FCIII only.
Bit 22 Enable Mailbox IRQ. FCIII only. Used by the internal RISC core.
Bits 31-23 Reserved.
The 32 HW PIDs: (Applies to FCIIB and FCIII)
Reg 0x310
Bits 4-0 PID index. (PIDs are read/write through 0x314).
Bits 7-5 Debug register index. FCIII only
Bit 8 Select which portion of the section filter to write to. (Only used when the
internal demux is used).
Bit 9 Pass all-tables. (Only used when the internal demux is used, no match
table-id). FCIII only
Reg 0x314
Bits 12-0 PID value
Bit 13 Enable internal demux. Should be set to 0 for the current skystar2.c
Bit 14 Enable this filter. This should be set to 1 to enable this filter.
As you can see, it is a little confusing. For the original 6 HW PIDs, you must have
Bits 13 and 14 not set or '0' and enable the respective bit in register 0x208 in order
to enable the PID.
For the 32 HW pids, you must have Bit 13 no set or '0' and bit 14 set or '1' in order
to enable the PID.
To make things a little more complicated, the extra bits in the above registers are
used for debugging and some internal status on the FCIII chip. They must be mask out.
All chips have an internal demux. It's only used in embedded applications or in the
case of FCIII for the USB product. They all have an internal RISC core, but only FCIII
is programmable.
Hope this clarifies all information I have written before. Please let me know if there
are any thing I can further clarify.
Augusto
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