Hi!
*********** REPLY SEPARATOR ***********
On 12/11/2003 at 11:34 AM Niklas Peinecke wrote:
>Augusto Cardoso wrote:
>> Hi!
>>
>> Here are the registers for the "two line serial":
>>
>> Reg 0x100
>> WRITE
>> Bits 6-0 CHIPADDRESS
>> Bit 7 Reserved
>> Bits 15-8 BASE ADDRESS
>> Bits 23-16 DATA1
>> Bit 24 Start transaction.
>> Bit 25 R/#W Read=1, Write=0
>> Bit 27-26 Size of transaction. 00=1, 11=4 bytes.
>> Bit 29-28 Port selection 00=Invalid, 01=Frontend, 10-EEPROM, 11=Tuner
>> Bit 30 Base address presence indicator. When 1, no base address is
>generated.
>> Bit 31 Reserved
>>
>> Reg 0x100
>> READ
>> Bit 0 R/#W - Internal states.
>> Bits 7-1 CHIPADDRESS
>> Bits 15-8 BASE ADDRESS
>> Bits 23-16 DATA1
>> Bit 24 Status. When=1, transaction underway. =0 engine is free.
>> Bit 25 R/#W Read=1, Write=0
>> Bit 27-26 Size of transaction. 00=1, 11=4 bytes.
>> Bit 29-28 Port selection 00=Invalid, 01=Frontend, 10-EEPROM, 11=Tuner
>> Bit 30 ACK error. When =1, no ACK from slave.
>> Bit 31 When set, it indicate that the current transaction is done.
>>
>> Reg 0x104
>> Bit 7-0 Data2
>> Bit 15-8 Data3
>> Bit 23-16 Data4
>> Bit 24 Explicit STOP. When set, the transaction is done without a
>trailing STOP. FC3 only.
>> Bit 25 When set, generates a STOP event. FC3 only.
>> Bit 31-26 Reserved.
>>
>> Reg 0x108, 0x10c and 0x110 Have the same function, but affecting ports
>1(Frontend), 2(EEPROM) and 3(Tuner), respectively.
>> Bits 5-0 thi Time High for i2c timing. The reference is a pre-scale
>internal clock based on the main clock.
>> Bits 12-8 tlo Time Low for i2c timing. The reference is a pre-scale
>internal clock based on the main clock.
>> All other bits, reserved.
>>
>> I hope this is not too confusing.
>> Let me know if you have any questions.
>>
>> Augusto
>>
>Ok, here I go:
>
> > Reg 0x100
> > WRITE
>...
> > Bits 15-8 BASE ADDRESS
>...
> > Bit 30 Base address presence indicator. When 1, no base address is
>generated.
>
>Does this mean when Bit 30 is set, the base address specified in 15-8 is
>not sent via i2c but only the DATA1, DATA2, and DATA3? Suppose I only
>want to send DATA1. Should I set size of transaction to 00 or 01 then? I
>suppose 00. Thus, there is no way to send 0 byte transactions ("i2c
>pings"), right? Also there is no way to do a read only from the bus,
>without writing the base address first (or is that the purpose of Bit 30)?
>
You are correct about all the above.
The Bit 30 won't generate the base address on a read.
You need to set it to 00 in order to send DATA1 only.
There is no way to do a "i2c ping" with flexcop.
>I hope, I do not ask for too much.
>
I'm glad you ask the questions, it makes me think about this and try to remember how
this suppose to work. :)
>Thanks,
>
>Niklas
>
>
>
>--
>
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