Oliver Endriss wrote:
>> @@ -340,11 +343,13 @@ static int stv0297_read_ber(struct dvb_f
>> struct stv0297_state *state = fe->demodulator_priv;
>> u8 BER[3];
>>
>> - stv0297_writereg(state, 0xA0, 0x80); // Start Counting bit errors
>> for 4096 Bytes
>> - mdelay(25); // Hopefully got 4096 Bytes
>> stv0297_readregs(state, 0xA0, BER, 3);
>> - mdelay(25);
>> - *ber = (BER[2] << 8 | BER[1]) / (8 * 4096);
>> + if (!(BER[0] & 0x80)) {
>> + state->last_ber = BER[2] << 8 | BER[1];
>> + stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
>> + }
>> +
>> + *ber = state->last_ber;
>>
>
> Hm - comparing the old code and the new one:
> Is BER[] the bit error *counter* or the bit error *rate*?
>
I think it is a counter. The counter is reset and counting starts, if
bit 7 in register 0xa0 is set. After ca. 90ms, counting stops and bit 7
is reset. I wrote a little piece of code, which stops the time and which
prints the values during and after the counting period.
> If it is a counter there is something missing.
>
What is missing?
> ... set bits 0 and 1 ...
> ... set bit 1, clear bit 0 ...
>
>> + stv0297_writereg_mask(state, 0xDF, 0x03, 0x01);
>>
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> ... clear bit 1, set bit 0 ...
>
> Looks suspicious to me. Is this correct?
>
>
It comes from stv0297_cs2.c:
stv0297_writeregI(state, RS_DESC_15, 0x03); /* freeze the
counters */
stv0297_redregsI(state, RS_DESC_0, block_count, 6);
stv0297_writeregI(state, RS_DESC_15, 0x03); /* clear the
counters */
stv0297_writeregI(state, RS_DESC_15, 0x03); /* re-enable the
counters */
Sorry, I didn't copy the comments. I've used stv0297_writereg_mask(),
because I don't know the meaning of register 0xDF and it seems that only
bit 0 and 1 are involved in the counters.
- Hartmut
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