Hi Ard,
On Fri, 29 Mar 2019 18:24:18 +0000,
Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
>
> The EFI stub is entered with the caches and MMU enabled by the
> firmware, and once the stub is ready to hand over to the decompressor,
> we clean and disable the caches.
>
> The cache clean routines use CP15 barrier instructions, which can be
> disabled via SCTLR. Normally, when using the provided cache handling
> routines to enable the caches and MMU, this bit is enabled as well.
> However, but since we entered the stub with the caches already enabled,
> this routine is not executed before we call the cache clean routines,
> resulting in undefined instruction exceptions if the firmware never
> enabled this bit.
>
> So set the bit explicitly in the EFI entry code.
>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> ---
> arch/arm/boot/compressed/head.S | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 6c7ccb428c07..62a49356fca3 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -1438,6 +1438,16 @@ ENTRY(efi_stub_entry)
>
> @ Preserve return value of efi_entry() in r4
> mov r4, r0
> +
> + @ our cache maintenance code relies on CP15 barrier instructions
> + @ but since we arrived here with the MMU and caches configured
> + @ by UEFI, we must ensure that the use of those instructions is
> + @ enabled in the SCTLR register, since we never executed our own
> + @ cache enable routine, which is normally in charge of this.
> + mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
> + orr r1, r1, #(1 << 5) @ CP15 barrier instructions
> + mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
> +
To be on the safe side, you could add an isb here. I'm pretty sure it
is immaterial on any ARMv7 core, but hey, I'm paranoid.
With that:
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
Thanks,
M.
--
Jazz is not dead, it just smell funny.
