On 5/26/26 6:42 AM, Theodore Tso wrote:
2. Host Controller Hardware Limits (UFSHCI)Transfer Queue Depth: A UFS controller supports a predefinednumber of outstanding task request entries. This is often hard-capped at 32 concurrent transfer requests (slots) by the doorbell register array.
The above information comes from the UFSHCI 3 standard. Jaegeuk's test setup has an UFSHCI 4.0 controller that supports one submission queue per CPU and also one completion queue per CPU. This is an architecture that is very similar but not identical to NVMe. Jaegeuk, please correct me if I got anything wrong. Bart. _______________________________________________ Linux-f2fs-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
