On 02/10/2014 10:52 AM, Laurent Pinchart wrote: > On Monday 10 February 2014 09:57:43 Stephen Warren wrote: >> On 02/10/2014 09:56 AM, Stephen Warren wrote: ... >>> I think the flag should represent the physical level of the signal on >>> the board at the device pin. I'm pretty sure that's what's most >>> consistent with existing DT properties. >> >> (That would have to be the GPIO source device, in order to account for >> any board-induced inversion) > > Would that be the physical level at the GPIO source device output to achieve > a > high level at the target device input pin, or the physical level at the GPIO > source device output to assert the signal at the target device input pin ? > The > first case wouldn't take the receiver device internal inverter into account > while the second case would. In the second case, how should we handle > receiver > devices that have configurable signal polarities (essentially > enabling/disabling the internal inverter from a software-controller > configuration) ?
I would expect the flag to represent the physical level that achieves (or represents, for inputs) a logically asserted value at the device. I don't think we should make the level flag influence any kind of configurable level within the device; that's a separate orthogonal, but related, concept. It'd be best if the DT binding for the device either (a) provided a separate property to configure that, or (b) picked a single one of the configurable values, and documented that all DTs should assume that value. -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
