2015-01-14 12:35 GMT+03:00 Linus Walleij <[email protected]>: > On Mon, Dec 22, 2014 at 11:05 AM, Dmitry Eremin-Solenikov > <[email protected]> wrote: > >> Low GPIO pins use an interrupt in SC interrupts space. However it's >> possible to handle them as if all the GPIO interrupts are instead tied >> to single GPIO handler, which later decodes GEDR register and >> chain-calls next IRQ handler. So split first 11 interrupts into system >> part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of >> system controller interrupts and real GPIO interrupts >> (IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then >> decodes and calls next handler. >> >> Signed-off-by: Dmitry Eremin-Solenikov <[email protected]> > > I applied all 5 patches and tested on the Compaq iPAQ H3600 > with some GPIO lines with IRQs and all work as before. > > Tested-by: Linus Walleij <[email protected]> > for all 5 patches.
Thank you! -- With best wishes Dmitry -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
