On Fri, Jun 04, 1999 at 09:30:19AM +0200, Lars Petterson wrote:
> Could you please explain what the PI2 and PackeTwin cards do wrong.
> I have thought about buying a, or manufacture my own, PI2 card so
> it could be nice to know what they lack.
In a DMA write cycle, the SCC wants the data to be valid
while /WR(SCC) is low. The ISA bus guarantees the data to be valid
only some time before the rising edge of /WR(ISA). Therefore, the
ISA bus data should be latched, and the /WR(SCC) pulse should
be generated thereafter. The PI2 doesn't latch the data, AFAIK.
It just delays the falling edge of /WR(ISA), which might not work
if you sometimes have long /WR(ISA) pulses.
If you have a PCI/ISA bridge in your PC, it fetches 32 bits at a
time from memory. If a new 32-bit word has to be fetched, it
usually takes some time until the data is valid. You will
sometimes transmit the old byte in the cache, i.e. byte (n-4)
instead of byte (n).
If your packets are long and the data rate is high (1Mbps or so),
you won't get a single packet out correctly.
I don't have a schematic of the Twin, but it has the same symptoms
on my ASUS mainboard.
The S5SCC/DMA card at least has the potential of doing it right,
I hopefully will be able to check that soon.
> How about DRSI and Baycom? I use a DRSI card at home, and our club
> stations two nodes uses DRSI-cards and two Baycom modems (I am the
> sysop of that system)
They don't have DMA at all, AFAIK.
> You can be very specific and technical, I have no problems with
> that as I work with electronics nowadays... :-)
Disclaimer: I haven't checked all this with a logic analyzer, it's
just the best explanation of the errors I see.
> 73 de Lars, sm6rpz
73 de Klaus OE1KIB/7J1BBB
