On Wed, Oct 11, 2023 at 03:34:03PM -0600, Gustavo A. R. Silva wrote:
> `struct clk_hw_onecell_data` is a flexible structure, which means that
> it contains flexible-array member at the bottom, in this case array
> `hws`:
>
> include/linux/clk-provider.h:
> 1380 struct clk_hw_onecell_data {
> 1381 unsigned int num;
> 1382 struct clk_hw *hws[] __counted_by(num);
> 1383 };
>
> This could potentially lead to an overwrite of the objects following
> `clk_data` in `struct stratix10_clock_data`, in this case
> `void __iomem *base;` at run-time:
>
> drivers/clk/socfpga/stratix10-clk.h:
> 9 struct stratix10_clock_data {
> 10 struct clk_hw_onecell_data clk_data;
> 11 void __iomem *base;
> 12 };
>
> There are currently three different places where memory is allocated for
> `struct stratix10_clock_data`, including the flex-array `hws` in
> `struct clk_hw_onecell_data`:
>
> drivers/clk/socfpga/clk-agilex.c:
> 469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> 470 num_clks), GFP_KERNEL);
>
> drivers/clk/socfpga/clk-agilex.c:
> 509 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> 510 num_clks), GFP_KERNEL);
>
> drivers/clk/socfpga/clk-s10.c:
> 400 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> 401 num_clks), GFP_KERNEL);
>
> I'll use just one of them to describe the issue. See below.
>
> Notice that a total of 440 bytes are allocated for flexible-array member
> `hws` at line 469:
>
> include/dt-bindings/clock/agilex-clock.h:
> 70 #define AGILEX_NUM_CLKS 55
>
> drivers/clk/socfpga/clk-agilex.c:
> 459 struct stratix10_clock_data *clk_data;
> 460 void __iomem *base;
> ...
> 466
> 467 num_clks = AGILEX_NUM_CLKS;
> 468
> 469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> 470 num_clks), GFP_KERNEL);
>
> `struct_size(clk_data, clk_data.hws, num_clks)` above translates to
> sizeof(struct stratix10_clock_data) + sizeof(struct clk_hw *) * 55 ==
> 16 + 8 * 55 == 16 + 440
> ^^^
> |
> allocated bytes for flex-array `hws`
>
> 474 for (i = 0; i < num_clks; i++)
> 475 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
> 476
> 477 clk_data->base = base;
>
> and then some data is written into both `hws` and `base` objects.
>
> Fix this by placing the declaration of object `clk_data` at the end of
> `struct stratix10_clock_data`. Also, add a comment to make it clear
> that this object must always be last in the structure.
>
> Fixes: ba7e258425ac ("clk: socfpga: Convert to s10/agilex/n5x to use clk_hw")
> Cc: [email protected]
> Signed-off-by: Gustavo A. R. Silva <[email protected]>
Nice find!
Reviewed-by: Kees Cook <[email protected]>
--
Kees Cook
