From: Claudiu Beznea <claudiu.beznea...@bp.renesas.com>
Hi,
Series adds initial USB support for the Renesas RZ/G3S SoC.
Series is split as follows:
- patches 01-03/12 - add signal support on SYSC driver support; this is
necessary for USB PHY as the USB PHY driver needs to
touch a register in the SYSC address space, in the
initialization phase
- patches 04-05/12 - updates the USB PHY documentation
- patches 06-07/12 - updates the USB PHY driver with a fix and the
support for PWRRDY SYSC signal
- patches 08-10/12 - updates the rzg2l-usbphy-ctrl driver and documentation
with support for the USB PWRRDY signal
- patches 11-12/12 - add device tree support
Merge strategy, if any:
- patches 01-03/12,11-12/12 can go through Renesas tree
- patches 04-07/12 can go through the PHY tree
- patches 08-10/12 can go through the reset tree
Thank you,
Claudiu Beznea
Changes in v3:
- as the basics of the SYSC driver was integrated, only the signal support
was preserved in this series, in a separate patch; patch 01/12 was
adjusted (by addressing the review comments received at [1]) as it is
necessary to build the signal support on top of it
- after long discussions with the internal HW team it has been confirmed
that the relation b/w individual USB specific HW blocks and signals
is like:
┌──────────────────────────────┐
│ │◄──
CPG_CLKON_USB.CLK0_ON
│ USB CH0 │
┌──────────────────────────┐ │┌───────────────────────────┐ │◄──
CPG_CLKON_USB.CLK2_ON
│ ┌────────┐ ││host controller registers │ │
│ │ │ ││function controller registers│
│ │ PHY0 │◄──┤└───────────────────────────┘ │
│ USB PHY │ │ └────────────▲─────────────────┘
│ └────────┘ │
│ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
│┌──────────────┐ ┌────────┐
││USBPHY control│ │ │
││ registers │ │ PHY1 │ ┌──────────────────────────────┐
│└──────────────┘ │ │◄──┤ USB CH1 │
│ └────────┘ │┌───────────────────────────┐ │◄──
CPG_CLKON_USB.CLK1_ON
└─▲───────▲─────────▲──────┘ ││ host controller registers │ │
│ │ │ │└───────────────────────────┘ │
│ │ │ └────────────▲─────────────────┘
│ │ │ │
│ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
│PWRRDY │ │
│ │ CPG_CLK_ON_USB.CLK3_ON
│ │
│ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
│
┌────┐
│SYSC│
└────┘
where:
- CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
of different USB blocks, X in {0, 1, 2, 3}
- CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
MSTOP of different USB blocks, X in {4, 5, 6, 7}
- USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
by the USB CH0, USB CH1
- SYSC is the system controller block controlling the PWRRDY signal
- USB CHx are individual USB block with host and function capabilities
(USB CH0 have both host and function capabilities, USB CH1 has only
host capabilities)
Due to this, the PWRRDY signal was also passed to the reset-rzg2l-usbphy-ctrl
reset driver (as it controls the USBPHY control registers) and these
are in the USB PHY block controlled by PWRRDY signal.
The PWRRDY signal need to be de-asserted on probe before enabling the module
clocks and the module MSTOP. To avoid any violation of this configuration
sequence, the PWRRDY signal is now controlled by USB PHY driver and the
reset-rzg2l-usbphy-ctrl driver.
As the PHYs gets reset signals from the USB reset controller driver, the
reset-rzg2l-usbphy-ctrl is probed before the USB PHY driver and thus,
in theory, we can drop the signal support (reference counting of the
USB PWRRDY) and configure the USB PWRRDY just in the reset-rzg2l-usbphy-ctrl.
However, to have a proper description of the diagram described above in
device tree and ensure the configuration sequence b/w PRWRDY, CLK and MSTOP
is preserved, the PWRRDY signal is controlled in this series in all the
drivers that work with registers from the USB PHY block.
Please provide your feedback on this solution.
Thank you,
Claudiu
[1]
https://lore.kernel.org/all/20250330214945.185725-2-john.madieu...@bp.renesas.com/
Changes in v2:
- dropped v1 patches already applied
- added fixes patches (07/14 and 09/14)
- dropped the approach of handling the USB PWRRDY though a reset controller
driver and introduced the signal concept for the SYSC driver; because
of this, most of the work done in v1 was dropped
- per patch changes are listed in individual patches, if any
Christophe JAILLET (1):
phy: renesas: rcar-gen3-usb2: Fix an error handling path in
rcar_gen3_phy_usb2_probe()
Claudiu Beznea (10):
soc: renesas: rz-sysc: Add signal support
soc: renesas: r9a08g045-sysc: Add USB PWRRDY signal
dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
dt-bindings: phy: renesas,usb2-phy: Add renesas,sysc-signals
phy: renesas: rcar-gen3-usb2: Add support for USB PWRRDY signal
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY signal
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
arm64: dts: renesas: r9a08g045: Add USB support
arm64: dts: renesas: rzg3s-smarc: Enable USB support
John Madieu (1):
soc: renesas: rz-sysc: Add syscon/regmap support
.../bindings/phy/renesas,usb2-phy.yaml | 23 ++
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 38 +++-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 120 +++++++++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 +++++
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 51 ++++-
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 46 ++++
drivers/soc/renesas/Kconfig | 1 +
drivers/soc/renesas/r9a08g045-sysc.c | 25 +++
drivers/soc/renesas/r9a09g047-sys.c | 13 ++
drivers/soc/renesas/r9a09g057-sys.c | 13 ++
drivers/soc/renesas/rz-sysc.c | 200 +++++++++++++++++-
drivers/soc/renesas/rz-sysc.h | 38 ++++
include/linux/soc/renesas/rz-sysc.h | 30 +++
13 files changed, 646 insertions(+), 9 deletions(-)
create mode 100644 include/linux/soc/renesas/rz-sysc.h
--
2.43.0
