On Mon, Aug 11, 2025 at 3:25 PM Thomas Richard <thomas.rich...@bootlin.com> wrote:
> This enables the pin control support of the onboard FPGA on AAEON UP > boards. > > This FPGA acts as a level shifter between the Intel SoC pins and the pin > header, and also as a mux or switch. > > +---------+ +--------------+ +---+ > | | | | | > | PWM0 | \ | | H | > |----------|------ \-----|-------------| E | > | I2C0_SDA | | | A | > Intel SoC |----------|------\ | | D | > | GPIO0 | \------|-------------| E | > |----------|------ | | R | > | | FPGA | | | > ----------+ +--------------+ +---+ > > For most of the pins, the FPGA opens/closes a switch to enable/disable > the access to the SoC pin from a pin header. > Each switch, has a direction flag that is set depending the status of the > SoC pin. > > For some other pins, the FPGA acts as a mux, and routes one pin (or the > other one) to the header. > > The driver also provides a GPIO chip. It requests SoC pins in GPIO mode, > and drives them in tandem with FPGA pins (switch/mux direction). > > This commit adds support only for UP Squared board. > > Reviewed-by: Linus Walleij <linus.wall...@linaro.org> > Reviewed-by: Andy Shevchenko <andriy.shevche...@linux.intel.com> > Acked-by: Linus Walleij <linus.wall...@linaro.org> > Signed-off-by: Thomas Richard <thomas.rich...@bootlin.com> This patch applied on top of the pile I pulled in from Bartosz! Yours, Linus Walleij
