This commit adds PECI bus/adapter node of AST24xx/AST25xx into
aspeed-g4 and aspeed-g5.

Signed-off-by: Jae Hyun Yoo <[email protected]>
Reviewed-by: Haiyue Wang <[email protected]>
Reviewed-by: James Feist <[email protected]>
Reviewed-by: Vernon Mauery <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Joel Stanley <[email protected]>
Cc: Andrew Jeffery <[email protected]>
Cc: Jason M Biils <[email protected]>
Cc: Ryan Chen <[email protected]>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 26 ++++++++++++++++++++++++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 26 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 680336ac06f8..1177c76a8a9d 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -29,6 +29,7 @@
                serial3 = &uart4;
                serial4 = &uart5;
                serial5 = &vuart;
+               peci0 = &peci0;
        };
 
        cpus {
@@ -311,6 +312,13 @@
                                };
                        };
 
+                       peci: peci@1e78b000 {
+                               compatible = "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0x0 0x1e78b000 0x60>;
+                       };
+
                        uart2: serial@1e78d000 {
                                compatible = "ns16550a";
                                reg = <0x1e78d000 0x20>;
@@ -354,6 +362,24 @@
        };
 };
 
+&peci {
+       peci0: peci-bus@0 {
+               compatible = "aspeed,ast2400-peci";
+               reg = <0x0 0x60>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <15>;
+               clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+               resets = <&syscon ASPEED_RESET_PECI>;
+               clock-frequency = <24000000>;
+               msg-timing = <1>;
+               addr-timing = <1>;
+               rd-sampling-point = <8>;
+               cmd-timeout-ms = <1000>;
+               status = "disabled";
+       };
+};
+
 &i2c {
        i2c_ic: interrupt-controller@0 {
                #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 02e70ad3ab70..f93f174bc149 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -29,6 +29,7 @@
                serial3 = &uart4;
                serial4 = &uart5;
                serial5 = &vuart;
+               peci0 = &peci0;
        };
 
        cpus {
@@ -370,6 +371,13 @@
                                };
                        };
 
+                       peci: peci@1e78b000 {
+                               compatible = "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0x0 0x1e78b000 0x60>;
+                       };
+
                        uart2: serial@1e78d000 {
                                compatible = "ns16550a";
                                reg = <0x1e78d000 0x20>;
@@ -413,6 +421,24 @@
        };
 };
 
+&peci {
+       peci0: peci-bus@0 {
+               compatible = "aspeed,ast2500-peci";
+               reg = <0x0 0x60>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <15>;
+               clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+               resets = <&syscon ASPEED_RESET_PECI>;
+               clock-frequency = <24000000>;
+               msg-timing = <1>;
+               addr-timing = <1>;
+               rd-sampling-point = <8>;
+               cmd-timeout-ms = <1000>;
+               status = "disabled";
+       };
+};
+
 &i2c {
        i2c_ic: interrupt-controller@0 {
                #interrupt-cells = <1>;
-- 
2.18.0

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