> From: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> > Sent: Friday, June 27, 2025 8:35 PM > [...] > Add DeviceTree bindings to enumerate the wakeup mailbox used in platform > firmware for Intel processors. > > x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert > followed by Start-Up IPI messages. The wakeup mailbox can be used when this > mechanism is unavailable. > > The wakeup mailbox offers more control to the operating system to boot > secondary CPUs than a spin-table. It allows the reuse of same wakeup vector > for all CPUs while maintaining control over which CPUs to boot and when. > While it is possible to achieve the same level of control using a spin- > table, it would require to specify a separate `cpu-release-addr` for each > secondary CPU. > > The operation and structure of the mailbox is described in the > Multiprocessor Wakeup Structure defined in the ACPI specification. Note > that this structure does not specify how to publish the mailbox to the > operating system (ACPI-based platform firmware uses a separate table). No > ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. > > Add a `compatible` property that the operating system can use to discover > the mailbox. Nodes wanting to refer to the reserved memory usually define a > `memory-region` property. /cpus/cpu* nodes would want to refer to the > mailbox, but they do not have such property defined in the DeviceTree > specification. Moreover, it would imply that there is a memory region per > CPU. > > Co-developed-by: Yunhong Jiang <yunhong.ji...@linux.intel.com> > Signed-off-by: Yunhong Jiang <yunhong.ji...@linux.intel.com> > Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> > ---
LGTM Reviewed-by: Dexuan Cui <de...@microsoft.com>
